公开(公告)号：US07629199B2

公开(公告)日：2009-12-08

申请号：US11713362

申请日：2007-03-01

Applicant: Chien-Ping Huang ,  Yu-Po Wang

Inventor： Chien-Ping Huang ,  Yu-Po Wang

IPC: H01L21/00

CPC classification number: H01L24/10 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.

Abstract translation: 提供了一种形成在芯片上的积层的半导体封装以及半导体封装的制造方法。 在其接合焊盘上形成有多个导电凸块的芯片被容纳在载体的空腔内，并且介电层封装其端部露出的导电凸块。 多个导电迹线形成在电介质层上并与导电凸块的端部电连接。 焊接掩模层施加在导电迹线上并形成有开口，通过该开口，导电迹线的预定部分暴露并结合到多个焊球。 因此，接合焊盘的位置容易地被导电凸块的露出端识别和区分，使得导电迹线能够通过导电凸块与接合焊盘良好地电连接，以提高制造的封装的产量。

公开(公告)号：US07271493B2

公开(公告)日：2007-09-18

申请号：US11112108

申请日：2005-04-21

Applicant: Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L29/40

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20070164386A1

公开(公告)日：2007-07-19

申请号：US11648045

申请日：2006-12-28

Applicant: Cheng-Yi Chang ,  Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

Inventor： Cheng-Yi Chang ,  Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

IPC: H01L31/0203 ,  H01L21/56

CPC classification number: H01L27/14687 ,  H01L24/97 ,  H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2224/85 ,  H01L2924/00014

Abstract: A semiconductor device and the fabrication method thereof are provided. The fabrication method includes providing a substrate module plate having a plurality of substrates; attaching at least one sensor chip to each of the substrates of the substrate module plate; electrically connecting each of the sensor chips to each of the substrates through bonding wires; forming an insulating layer between each sensor chip on the substrate module plate, wherein the height of the insulating layers are not greater than the thickness of the sensor chips so as to prevent flash from the insulating layers from contaminating the sensor chips; forming an adhesive lip on the insulating layer or forming a second insulating layer followed by forming the adhesive layer, wherein the adhesive layer or the second insulating layer is higher than the highest loop-height of the bonding wires; adhering a light transmitting cover to each adhesive layer to cover the sensor chip; and cutting the substrate module plate to separate the substrates to form a plurality of semiconductor devices each integrated with at least one sensor chip. As the adhesive layers are not in contact with the bonding wires, the problems of damaging or breaking the bonding wires can be prevented in the process of adhering the light transmitting cover.

Abstract translation: 提供半导体器件及其制造方法。 该制造方法包括提供具有多个基板的基板模块板; 将至少一个传感器芯片附接到所述基板模块板的每个基板; 通过接合线将每个传感器芯片电连接到每个基板; 在衬底模块板上的每个传感器芯片之间形成绝缘层，其中绝缘层的高度不大于传感器芯片的厚度，以防止来自绝缘层的闪光污染传感器芯片; 在所述绝缘层上形成粘合剂唇缘或形成第二绝缘层，接着形成所述粘合剂层，其中所述粘合剂层或所述第二绝缘层高于所述接合线的最高环高度; 将透光盖粘附到每个粘合剂层以覆盖传感器芯片; 以及切割所述基板模块板以分离所述基板以形成多个半导体器件，每个半导体器件与至少一个传感器芯片集成。 由于粘合层不与接合线接触，所以在粘接透光罩的过程中可以防止损坏或断裂接合线的问题。

公开(公告)号：US20050258537A1

公开(公告)日：2005-11-24

申请号：US10632709

申请日：2003-07-31

Applicant: Chien-Ping Huang ,  Yu-Po Wang

Inventor： Chien-Ping Huang ,  Yu-Po Wang

IPC: H01L21/48 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/10 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.

Abstract translation: 提供了一种形成在芯片上的积层的半导体封装以及半导体封装的制造方法。 在其接合焊盘上形成有多个导电凸块的芯片被容纳在载体的空腔内，并且介电层封装其端部露出的导电凸块。 多个导电迹线形成在电介质层上并与导电凸块的端部电连接。 焊接掩模层施加在导电迹线上并形成有开口，通过该开口，导电迹线的预定部分暴露并结合到多个焊球。 因此，接合焊盘的位置容易地被导电凸块的露出端识别和区分，使得导电迹线能够通过导电凸块与接合焊盘良好地电连接，以提高制造的封装的产量。

公开(公告)号：US07679178B2

公开(公告)日：2010-03-16

申请号：US11974441

申请日：2007-10-12

Applicant: Han-Ping Pu ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Han-Ping Pu ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L23/02

CPC classification number: H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16151 ,  H01L2924/16195 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor package on which a semiconductor device can be stacked and fabrication method thereof are provided. The fabrication method includes the steps of mounting and electrically connecting at least one semiconductor chip on the substrate, mounting an electrical connecting structure consisting of an upper layer circuit board and a lower layer circuit board on the substrate and electrically connecting the electrical connecting structure to the substrate, where the semiconductor chip is received in a receiving space formed in the electrical connecting structure; forming an encapsulant on the substrate encapsulating the semiconductor chip and the electrical connecting structure, and after the encapsulant is formed, exposing top surface of the upper layer circuit board with a plurality of solder pads from the encapsulant to allow at least one semiconductor device to electrically connect the upper layer circuit board so as to form a stack structure.

Abstract translation: 提供半导体器件可堆叠的半导体封装件及其制造方法。 该制造方法包括以下步骤：在基板上安装和电连接至少一个半导体芯片，将由上层电路板和下层电路板组成的电连接结构安装在基板上，并将电连接结构电连接到 衬底，其中所述半导体芯片被容纳在形成在所述电连接结构中的接收空间中; 在封装半导体芯片和电连接结构的基板上形成密封剂，并且在形成密封剂之后，用来自密封剂的多个焊盘将上层电路板的顶表面曝光，以允许至少一个半导体器件电 连接上层电路板，形成堆叠结构。

公开(公告)号：US20090008801A1

公开(公告)日：2009-01-08

申请号：US12217365

申请日：2008-07-02

Applicant: Jeng-Yuan Lai ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Yu-Po Wang ,  Chiao-Hung Yen

Inventor： Jeng-Yuan Lai ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Yu-Po Wang ,  Chiao-Hung Yen

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H05K1/0206 ,  H01L21/50 ,  H01L21/563 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/4985 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H05K1/0209 ,  H05K1/189 ,  H05K2201/09781 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00014

Abstract: This invention discloses a semiconductor device and a method for fabricating the same. The method includes providing a flexible carrier board having a first surface and a second surface opposite thereto; forming a metal lead layer and a first heat dissipating metal layer on the first surface of the flexible carrier board, and forming a second heat dissipating metal layer on the second surface of the flexible carrier board; providing a chip having an active surface and an opposed non-active surface, wherein a plurality of solder pads are formed on the active surface of the chip, each of the solder pads has a metal bump formed thereon and corresponding in position to the metal lead layer, and heat dissipating bumps are formed between the metal bumps corresponding in position to the first heat dissipating metal layer.

Abstract translation: 本发明公开了一种半导体器件及其制造方法。 该方法包括提供具有第一表面和与其相对的第二表面的柔性载体板; 在柔性载体板的第一表面上形成金属引线层和第一散热金属层，并在柔性载体板的第二表面上形成第二散热金属层; 提供具有活性表面和相对的非活性表面的芯片，其中在芯片的有源表面上形成多个焊盘，每个焊盘在其上形成金属凸块，并且在金属引线的对应位置 在与第一散热金属层的位置对应的金属凸块之间形成有散热凸块。

公开(公告)号：US20090004784A1

公开(公告)日：2009-01-01

申请号：US12204066

申请日：2008-09-04

Applicant: Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L21/56

CPC classification number: H01L21/4832 ,  H01L21/4857 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20080185725A1

公开(公告)日：2008-08-07

申请号：US12011854

申请日：2008-01-30

Applicant: Wen Cheng Lee ,  Chien-Ping Huang ,  Yu-Po Wang ,  Wei-Chun Lin

Inventor： Wen Cheng Lee ,  Chien-Ping Huang ,  Yu-Po Wang ,  Wei-Chun Lin

IPC: H01L23/482

CPC classification number: H01L23/49838 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor substrate having a body and a plurality of finger pads formed thereon is disclosed. Each of the finger pads includes two expanding portions respectively and a connecting portion formed therebetween. The finger pads are alternately arranged on the body in a manner that one of the expanding portions of one of the finger pads is disposed in position corresponding to the connecting portion of an adjacent one of the finger pads, so as to reduce pitches between the finger pads horizontally and vertically, provide sufficient spaces for wire bonding, and prevent a wire bonder from mistakenly recognizing a lead trace coupled to the finger pad as another finger pad.

Abstract translation: 公开了一种具有主体和形成在其上的多个指垫的半导体衬底。 每个指垫分别包括两个膨胀部分和在它们之间形成的连接部分。 手指垫以这样的方式交替地布置在主体上，使得一个指垫的一个扩展部分设置在与相邻的一个指垫的连接部分相对应的位置，以便减小手指之间的间距 水平和垂直地提供垫片，为引线接合提供足够的空间，并且防止引线接合器错误地识别作为另一个手指垫耦合到指垫的引线迹线。

公开(公告)号：US07354796B2

公开(公告)日：2008-04-08

申请号：US11821269

申请日：2007-06-22

Applicant: Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L21/00

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US07342318B2

公开(公告)日：2008-03-11

申请号：US11112145

申请日：2005-04-21

Applicant: Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L29/40

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/58 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K3/007 ,  H05K3/3457 ,  H05K3/4682 ,  H05K2203/0152 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。