发明授权
- 专利标题： Calculating method, verification method, verification program and verification system for edge deviation quantity, and semiconductor device manufacturing method
- 专利标题（中）： 边缘偏移量的计算方法，验证方法，验证程序和验证系统以及半导体器件制造方法
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申请号： US11727288申请日： 2007-03-26
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公开(公告)号： US07631287B2公开(公告)日： 2009-12-08
- 发明人: Kyoko Izuha , Toshiya Kotani , Satoshi Tanaka
- 申请人： Kyoko Izuha , Toshiya Kotani , Satoshi Tanaka
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权： JP2003-074821 20030319
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge of the finish pattern and the desired pattern is calculated, comprising setting a reference light beam intensity for setting the desired pattern on a wafer, setting an evaluation point for comparison of the finish pattern with the desired pattern, calculating a light beam intensity at the evaluation point, calculating a differentiation value of the light beam intensity at the evaluation point, calculating an intersection of the differentiation value with the reference light beam intensity, and calculating a difference between the intersection and the evaluation point, the difference defining an edge deviation quantity of the finish pattern from the desired pattern.
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