Invention Grant
- Patent Title: Method of manufacturing wafer level package
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Application No.: US12149106Application Date: 2008-04-25
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Publication No.: US07632709B2Publication Date: 2009-12-15
- Inventor: Hyung-Jin Jeon , Sung Yi , Young-Do Kweon , Jong-Yun Lee , Joon-Seok Kang , Seung-Wook Park
- Applicant: Hyung-Jin Jeon , Sung Yi , Young-Do Kweon , Jong-Yun Lee , Joon-Seok Kang , Seung-Wook Park
- Applicant Address: KR Suwon
- Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee Address: KR Suwon
- Priority: KR10-2007-0099228 20071002
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.
Public/Granted literature
- US20090087951A1 Method of manufacturing wafer level package Public/Granted day:2009-04-02
Information query
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