Invention Grant
- Patent Title: Method for dual damascene process
- Patent Title (中): 双镶嵌工艺的方法
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Application No.: US11687093Application Date: 2007-03-16
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Publication No.: US07642184B2Publication Date: 2010-01-05
- Inventor: Ching-Yu Chang , Jen-Chieh Shih
- Applicant: Ching-Yu Chang , Jen-Chieh Shih
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
The present disclosure provides a method of dual damascene processing. The method includes providing a substrate having vias formed therein; forming an under-layer in the vias and on the substrate; applying a solvent washing process to the under-layer; forming a silicon contained layer on the under-layer; patterning the silicon contained layer (SCL) to form SCL openings exposing the under-layer within the SCL openings; and etching the substrate and the under-layer within the SCL openings to form trenches.
Public/Granted literature
- US20080227287A1 Method For Dual Damascene Process Public/Granted day:2008-09-18
Information query
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