发明授权
US07642800B2 Wafer test system wherein period of high voltage stress test of one chip overlaps period of function test of other chip
有权
晶片测试系统，其中一个芯片的高压应力测试周期与其他芯片的功能测试周期重叠
- 专利标题： Wafer test system wherein period of high voltage stress test of one chip overlaps period of function test of other chip
- 专利标题（中）： 晶片测试系统，其中一个芯片的高压应力测试周期与其他芯片的功能测试周期重叠
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申请号： US11848954申请日： 2007-08-31
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公开(公告)号： US07642800B2公开(公告)日： 2010-01-05
- 发明人: Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
- 申请人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
- 申请人地址： TW Tainan County
- 专利权人： Himax Technologies Limited
- 当前专利权人： Himax Technologies Limited
- 当前专利权人地址： TW Tainan County
- 代理机构： J.C. Patents
- 主分类号： G01R31/02
- IPC分类号： G01R31/02 ; G01R31/26
摘要：
A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.
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