发明授权
- 专利标题: Method for fabricating semiconductor package with stacked chips
- 专利标题(中): 制造具有堆叠芯片的半导体封装的方法
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申请号: US11649144申请日: 2007-01-02
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公开(公告)号: US07655503B2公开(公告)日: 2010-02-02
- 发明人: Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
- 申请人: Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
- 申请人地址: TW
- 专利权人: Siliconware Precision Industries Co., Ltd.
- 当前专利权人: Siliconware Precision Industries Co., Ltd.
- 当前专利权人地址: TW
- 代理机构: Edwards Angell Palmer & Dodge LLP
- 代理商 Peter F. Corless; Steven M. Jensen
- 优先权: TW93123055A 20040802
- 主分类号: H01L21/50
- IPC分类号: H01L21/50
摘要:
A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.
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