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    Multi-chip stack structure and fabricating method thereof
    2.
    发明申请
    Multi-chip stack structure and fabricating method thereof 审中-公开
    多芯片堆叠结构及其制造方法

    公开(公告)号：US20090014860A1

    公开(公告)日：2009-01-15

    申请号：US12011832

    申请日：2008-01-29

    申请人： Chung-Lun Liu ,  Jung-Pin Huang ,  Chin-Huang Chang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    发明人： Chung-Lun Liu ,  Jung-Pin Huang ,  Chin-Huang Chang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    IPC分类号： H01L21/00 ,  H01L23/02

    CPC分类号： H01L25/0652 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00012

    摘要： A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products.

    摘要翻译： 提供了一种多芯片堆叠结构及其制造方法。 该制造方法包括以下步骤：提供具有与其相对的第一表面和第二表面的芯片载体和至少安装在第一表面上的第一芯片和第二芯片; 通过多个接合线将芯片电连接到芯片载体上; 并且通过其间放置的膜将第一和第二芯片上的至少第三芯片堆叠起来，其中第三芯片逐步堆叠在第一芯片上，并且连接到第二芯片的键合线的至少一部分被膜覆盖， 并通过接合线电连接第三芯片和芯片载体，从而能够将多个芯片堆叠在芯片载体上，以增强电子产品的电气性能。

    Semiconductor package with chip supporting member
    6.
    发明授权
    Semiconductor package with chip supporting member 失效
    半导体封装带芯片支撑件

    公开(公告)号：US06737737B1

    公开(公告)日：2004-05-18

    申请号：US10355610

    申请日：2003-01-31

    申请人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Jung-Pin Huang

    发明人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Jung-Pin Huang

    IPC分类号： H01L23495

    CPC分类号： H01L23/16 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A semiconductor package with a chip supporting member is provided, including a lead frame having a die pad and a plurality of leads, and a chip supporting member mounted on a central portion of the die pad. The chip supporting member has a first surface and an opposing second surface attached to the die pad. At least a chip is mounted on the first surface of the chip supporting member to space the chip apart from the die pad via the chip supporting member, so as to prevent the chip from being damaged by thermal stress induced by CTE (coefficient of thermal expansion) mismatch between the chip and lead frame, thereby eliminating delamination, warpage and chip cracks. Moreover, the chip supporting member interposed between the chip and die pad provides greater flexibility for mounting variously sized or shaped chips on the die pad without having to use chips corresponding to profile of the die pad.

    摘要翻译： 提供一种具有芯片支撑构件的半导体封装，包括具有管芯焊盘和多个引线的引线框架，以及安装在管芯焊盘的中心部分的芯片支撑构件。 芯片支撑构件具有附接到管芯焊盘的第一表面和相对的第二表面。 至少芯片安装在芯片支撑部件的第一表面上，以通过芯片支撑部件将芯片与芯片焊盘隔开，以防止芯片被CTE引起的热应力（热膨胀系数 ）芯片和引线框架之间的不匹配，从而消除分层，翘曲和芯片裂纹。 此外，插入在芯片和芯片焊盘之间的芯片支撑构件提供了更大的灵活性，用于在芯片焊盘上安装各种尺寸或形状的芯片，而不必使用对应于芯片焊盘轮廓的芯片。

    MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA
    8.
    发明申请
    MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA 审中-公开
    通过硅的多芯片堆叠结构

    公开(公告)号：US20110227226A1

    公开(公告)日：2011-09-22

    申请号：US13151823

    申请日：2011-06-02

    申请人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

    发明人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

    IPC分类号： H01L23/48

    CPC分类号： H01L29/0657 ,  H01L23/481 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599

    摘要： The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier.

    摘要翻译： 本发明公开了一种通过硅通孔的多芯片堆叠结构及其制造方法。 该方法包括：提供具有多个第一芯片的晶片; 在每个所述第一芯片的第一表面上形成多个孔，并形成对应于所述孔的金属柱和焊盘，以形成贯穿硅通孔（TSV）结构; 在所述第一芯片的每一个的第二表面上形成至少一个凹槽以暴露所述TSV结构的所述金属柱，以允许至少一个第二芯片堆叠在所述第一芯片上，被接收在所述凹槽中并电连接到 从槽露出的金属柱; 用绝缘材料填充凹槽以封装第二芯片; 将导电元件安装在每个第一芯片的第一表面的焊盘上并分离晶片; 并且经由导电元件将堆叠的第一和第二芯片安装并电连接到芯片载体。 不是完全变薄但包括多个第一芯片的晶片在制造过程中切断了承载目的，从而解决了面临现有技术需要重复使用的问题，即复杂的工艺，高成本和粘合剂层污染 的载体板和用于垂直堆叠多个芯片的粘合剂层，并将堆叠的芯片安装在芯片载体上。