Invention Grant
US07660377B2 Device for estimating a timing correction loop error for a digital demodulator
有权
用于估计数字解调器的定时校正回路误差的装置
- Patent Title: Device for estimating a timing correction loop error for a digital demodulator
- Patent Title (中): 用于估计数字解调器的定时校正回路误差的装置
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Application No.: US11270388Application Date: 2005-11-09
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Publication No.: US07660377B2Publication Date: 2010-02-09
- Inventor: Jacques Meyer
- Applicant: Jacques Meyer
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics S.A.
- Current Assignee: STMicroelectronics S.A.
- Current Assignee Address: FR Montrouge
- Agency: Wolf, Greenfield & Sacks, P.C.
- Agent Lisa K. Jorgenson; William R. McClellan
- Priority: FR0452576 20041109
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A device for providing a digital error signal, for a timing correction loop of a digital demodulator for digital transmission by phase modulation or amplitude and phase modulation, the device successively receiving pairs of digital signals representative of the components of complex signals, and having circuitry for providing a difference signal representative of the difference between the modulus of the complex signal corresponding to the last received pair of digital signals and the modulus of the complex signal corresponding to the previously-received pair of digital signals; circuitry for providing a weighting factor which depends on the angle between the complex signal corresponding to the last received pair of digital signals and the complex signal corresponding to the previously-received pair of digital signals; and circuitry for providing the error signal proportional to the product of the difference signal and of the weighting factor.
Public/Granted literature
- US20060098763A1 Device for estimating a timing correction loop error for a digital demodulator Public/Granted day:2006-05-11
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