Invention Grant
US07663516B1 Scheme for non-linearity correction of residue amplifiers in a pipelined analog-to-digital converter (ADC) 有权
流水线模数转换器(ADC)中残留放大器的非线性校正方案

  • Patent Title: Scheme for non-linearity correction of residue amplifiers in a pipelined analog-to-digital converter (ADC)
  • Patent Title (中): 流水线模数转换器(ADC)中残留放大器的非线性校正方案
  • Application No.: US12197347
    Application Date: 2008-08-25
  • Publication No.: US07663516B1
    Publication Date: 2010-02-16
  • Inventor: Gaurav Chandra
  • Applicant: Gaurav Chandra
  • Applicant Address: US TX Dallas
  • Assignee: Texas Instruments Incorporated
  • Current Assignee: Texas Instruments Incorporated
  • Current Assignee Address: US TX Dallas
  • Agent Ronald O. Neerings; Wade James Brady, III; Frederick J. Telecky, Jr.
  • Main IPC: H03M1/10
  • IPC: H03M1/10
Scheme for non-linearity correction of residue amplifiers in a pipelined analog-to-digital converter (ADC)
Abstract:
In a method and apparatus for compensating non-linearity of a gain of a residual amplifier (RA), a pipelined analog-to-digital converter (ADC) converts an analog input to a digital output (DO). The ADC includes a plurality of pipelined stages (PPS). Each stage, which includes an instance of the RA, provides a digital code corresponding to an output of the RA included in a preceding stage. A memory stores a piecewise linear representation for modeling the non-linearity of the gain. A calibrated gain of the RA corresponding to each region of a plurality of linear operating regions of the RA is stored in the memory. A gain adjuster adjusts the digital code for each one of the PPS in accordance with a gain factor derived from the calibrated gain for each one of the PPS. A constructor constructs the DO from the adjusted digital code received from each one of the PPS.
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