公开(公告)号：US07327997B2

公开(公告)日：2008-02-05

申请号：US10711724

申请日：2004-09-30

Applicant: Gaurav Chandra ,  Preetam Charan Anand Tadeparthy ,  Prakash Easwaran

Inventor： Gaurav Chandra ,  Preetam Charan Anand Tadeparthy ,  Prakash Easwaran

IPC: H04B1/10

CPC classification number: H03H11/126 ,  H04B1/16

Abstract: A trans-impedance filter circuit provided according to an aspect of the present invention contains an operational amplifier, a first resistor, a first capacitor, a second resistor, and a second capacitor. The second capacitor is connected in parallel between the inverting input terminal and an output path of the operational amplifier. The second resistor is connected between the output terminal of the operational amplifier and a second node on a path connecting the input signal to the inverting input terminal. The first resistor is coupled between the first node and inverting input terminal of the operational amplifier. The first capacitor is coupled between the first node and Vss. Due to such connections, the filter circuit operates as a second order filter circuit, thereby providing a desired high level of filtering. Also, as the filter circuit is implemented with a single operational amplifier, the power and area requirements are reduced.

Abstract translation: 根据本发明一方面提供的跨阻抗滤波器电路包括运算放大器，第一电阻器，第一电容器，第二电阻器和第二电容器。 第二电容器并联连接在反相输入端和运算放大器的输出路径之间。 第二电阻器连接在运算放大器的输出端和将输入信号连接到反相输入端的路径上的第二节点之间。 第一电阻耦合在运算放大器的第一节点和反相输入端之间。 第一电容器耦合在第一节点和Vss之间。 由于这种连接，滤波器电路作为二阶滤波器电路工作，从而提供期望的高级滤波。 而且，由于滤波器电路由单个运算放大器实现，所以功率和面积要求降低。

公开(公告)号：US20060103469A1

公开(公告)日：2006-05-18

申请号：US10904578

申请日：2004-11-17

Applicant: Gaurav CHANDRA ,  Prakash EASWARAN ,  Sumantra SETH

Inventor： Gaurav CHANDRA ,  Prakash EASWARAN ,  Sumantra SETH

IPC: H03F3/191

CPC classification number: H03F1/34 ,  H03G3/3052 ,  H03G5/24 ,  H03H11/126 ,  H03H11/1291

Abstract: A low distortion filter circuit implementing variable gain amplification (VGA). An aspect of the present invention increases the degrees of freedom (number of components which can be independently programmed/changed to corresponding desired values) to achieve a desired combination of D.C. gain and filter characteristics (e.g., corner frequency, Q-factor, notch frequency, etc.). Such additional degrees of freedom are attained by including additional components in either an input block or a feedback block (implemented with reference to an operational amplifier), and by redesigning the other block using principles such as admittance cancellation to remove the effects of such additional components. The blocks are designed such that a terminal of the programmable components is connected to a fixed/constant voltage (e.g., ground). Embodiments implementing bi-quad single amplifier with and without notch are disclosed.

Abstract translation: 实现可变增益放大（VGA）的低失真滤波电路。 本发明的一个方面增加了自由度（可以被独立地编程/改变为相应的期望值的分量的数量），以实现期望的DC增益和滤波器特性的组合（例如，转角频率，Q因子，陷波频率 等）。 这样的附加自由度通过将附加组件包括在输入块或反馈块（参考运算放大器实现）中来实现，并且通过使用诸如导纳消除之类的原理重新设计其他块来消除这些附加组件的影响 。 这些块被设计成使得可编程组件的端子连接到固定/恒定电压（例如，接地）。 公开了实现具有和没有陷波的双二极管单放大器的实施例。

公开(公告)号：US20060068741A1

公开(公告)日：2006-03-30

申请号：US10711680

申请日：2004-09-30

Applicant: Anant KAMATH ,  Gaurav CHANDRA ,  Prakash EASWARAN

Inventor： Anant KAMATH ,  Gaurav CHANDRA ,  Prakash EASWARAN

IPC: H04B1/10

CPC classification number: H04B1/30 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2203/45136 ,  H03F2203/45526

Abstract: A receiver, implemented with low noise and low distortion, to process an input signal containing signals of interest and unwanted interference signal. In an embodiment, the receiver contains a mixer which generates an intermediate signal in the form of an electric current, and a filter which filters the unwanted interference signals from the intermediate signal. The intermediate signal is centered around a lower frequency compared to a crier frequency of the input signal. Due to the current mode interface between the mixer and the filter circuit, low noise and low distortion may be attended.

Abstract translation: 以低噪声和低失真实现的接收机，用于处理包含感兴趣信号和不想要的干扰信号的输入信号。 在一个实施例中，接收机包含以电流形式产生中间信号的混频器和从中间信号滤除不想要的干扰信号的滤波器。 与输入信号的频率相比，中间信号以较低频率为中心。 由于混频器和滤波电路之间的电流模式接口，可能会出现低噪声和低失真。

公开(公告)号：US20110261863A1

公开(公告)日：2011-10-27

申请号：US12765097

申请日：2010-04-22

Applicant: Gaurav Chandra ,  Moshe Malkin ,  Dariush Dabiri

Inventor： Gaurav Chandra ,  Moshe Malkin ,  Dariush Dabiri

IPC: H04B1/40

CPC classification number: H04B3/23 ,  H04L5/1461 ,  H04M9/082

Abstract: Embodiments of a method and apparatus of reducing transmit signal components of a receive signal of a transceiver are disclosed. One method includes generating a transmit signal by passing a pre-driver transmit signal through a transmit driver. An echo cancellation signal is generated by passing the pre-driver transmit signal through an echo cancellation driver. A residual echo signal is generated by passing a pre-driver residual echo cancellation signal through a residual echo cancellation driver. The transceiver simultaneously transmits the transmit signal, and receiving the receive signal. At least a portion of an echo signal of the receive signal is canceled by summing the echo cancellation signal with the receive signal. At least another portion of the cancellation echo signal of the receive signal is canceled by summing the residual echo cancellation signal with the receive signal.

Abstract translation: 公开了一种降低收发器的接收信号的发射信号分量的方法和装置的实施例。 一种方法包括通过将预驱动器发送信号通过发送驱动器来产生发送信号。 通过将预驱动器发送信号通过回波消除驱动器来产生回波消除信号。 通过将预驱动器残留回声消除信号通过残余回声消除驱动器来产生残留回波信号。 收发器同时发送发送信号，并接收接收信号。 通过将回波消除信号与接收信号相加来消除接收信号的回波信号的至少一部分。 接收信号的消除回波信号的至少另一部分通过将残差回波消除信号与接收信号相加来消除。

公开(公告)号：US07719299B2

公开(公告)日：2010-05-18

申请号：US12061409

申请日：2008-04-02

Applicant: Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

Inventor： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

IPC: G01R31/02 ,  H01L21/66

CPC classification number: H03M3/35 ,  H01L22/34 ,  H03M3/43 ,  H03M3/438

Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.

Abstract translation: 在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。 监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。 如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。 使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。 数字信号以可配置的时间间隔存储以形成数字比特流。 将数字位流与参考值进行比较，以确定缺陷是否在允许范围内。

公开(公告)号：US20090267693A1

公开(公告)日：2009-10-29

申请号：US12109449

申请日：2008-04-25

Applicant: Gaurav Chandra ,  Danielle Lyn Griffith

Inventor： Gaurav Chandra ,  Danielle Lyn Griffith

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/45659 ,  H03F2203/45048 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45438 ,  H03F2203/45534 ,  H03F2203/45686 ,  H03F2203/45702

Abstract: In a method and apparatus for trimming values of load resistors to reduce variations there between, a common mode feedback loop (CMFBL) included in a differential amplifier is switched from operating in a closed loop mode to operate in an open loop mode. The CMFBL includes an operational amplifier (OA) generating an output signal. A selector switch, coupled to receive the output signal, is operable to switch a path of the output signal in response to a CAL signal. In the closed loop mode, the selector switch routes the output signal to a feedback loop to provide a regulated current to the load resistors. In the open loop mode, the OA operates as a comparator and the output signal is provided as a digital signal. The selector switch provides the digital signal to a controller to digitally trim the values of the load resistors.

Abstract translation: 在用于修整负载电阻器的值以减小其间的变化的方法和装置中，包括在差分放大器中的共模反馈环路（CMFBL）从闭环模式中操作切换到以开环模式操作。 CMFBL包括产生输出信号的运算放大器（OA）。 耦合以接收输出信号的选择器开关可用于响应于CAL信号切换输出信号的路径。 在闭环模式下，选择器开关将输出信号路由到反馈回路，以向负载电阻提供稳压电流。 在开环模式下，OA作为比较器运行，输出信号作为数字信号提供。 选择器开关为控制器提供数字信号，以数字修整负载电阻的值。

公开(公告)号：US20060068742A1

公开(公告)日：2006-03-30

申请号：US10711724

申请日：2004-09-30

Applicant: Gaurav CHANDRA ,  Preetam TADEPARTHY ,  Prakash EASWARAN

Inventor： Gaurav CHANDRA ,  Preetam TADEPARTHY ,  Prakash EASWARAN

IPC: H04B1/18 ,  H04B1/10

CPC classification number: H03H11/126 ,  H04B1/16

Abstract: A trans-impedance filter circuit provided according to an aspect of the present invention contains an operational amplifier, a first resistor, a first capacitor, a second resistor, and a second capacitor. The second capacitor is connected in parallel between the inverting input terminal and an output path of the operational amplifier. The second resistor is connected between the output terminal of the operational amplifier and a second node on a path connecting the input signal to the inverting input terminal. The first resistor is coupled between the first node and inverting input terminal of the operational amplifier. The first capacitor is coupled between the first node and Vss. Due to such connections, the filter circuit operates as a second order filter circuit, thereby providing a desired high level of filtering. Also, as the filter circuit is implemented with a single operational amplifier, the power and area requirements are reduced.

Abstract translation: 根据本发明一方面提供的跨阻抗滤波器电路包括运算放大器，第一电阻器，第一电容器，第二电阻器和第二电容器。 第二电容器并联连接在反相输入端和运算放大器的输出路径之间。 第二电阻器连接在运算放大器的输出端和将输入信号连接到反相输入端的路径上的第二节点之间。 第一电阻耦合在运算放大器的第一节点和反相输入端之间。 第一电容器耦合在第一节点和Vss之间。 由于这种连接，滤波器电路作为二阶滤波器电路工作，从而提供期望的高级滤波。 而且，由于滤波器电路由单个运算放大器实现，所以功率和面积要求降低。

公开(公告)号：US20100259429A1

公开(公告)日：2010-10-14

申请号：US12423667

申请日：2009-04-14

Applicant: Baher Haroun ,  Gaurav Chandra

Inventor： Baher Haroun ,  Gaurav Chandra

IPC: H03M1/10 ,  H03M1/66

CPC classification number: H03M1/1033 ,  H03M1/747

Abstract: Methods and apparatus for error cancelation in calibrated current sources are disclosed. In an example, a digital to analog converter to convert digital bits into an analog output signal is described, including a plurality of current sources, a calibrator, and a current source selector. The example current sources output substantially identical currents, and the calibrator is selectively coupled to sequentially calibrate the current sources to a reference current. The example current source selector assigns respective ones of the plurality of current sources to the digital bits in accordance with a bit-to-current source sequence selected to reduce current error in the analog output and changes the assignments based on the current source coupled to the calibrator.

Abstract translation: 公开了用于校准电流源中的误差消除的方法和装置。 在一个示例中，描述了将数字位转换为模拟输出信号的数模转换器，包括多个电流源，校准器和电流源选择器。 示例性电流源输出基本相同的电流，并且校准器被选择性地耦合以将电流源依次校准为参考电流。 示例性电流源选择器根据选择以减少模拟输出中的电流误差的位电流源序列将多个电流源中的相应电流源分配给数字位，并且基于耦合到 校准器

公开(公告)号：US07804433B1

公开(公告)日：2010-09-28

申请号：US12423667

申请日：2009-04-14

Applicant: Baher Haroun ,  Gaurav Chandra

Inventor： Baher Haroun ,  Gaurav Chandra

IPC: H03M1/10

CPC classification number: H03M1/1033 ,  H03M1/747

Abstract: Methods and apparatus for error cancelation in calibrated current sources are disclosed. In an example, a digital to analog converter to convert digital bits into an analog output signal is described, including a plurality of current sources, a calibrator, and a current source selector. The example current sources output substantially identical currents, and the calibrator is selectively coupled to sequentially calibrate the current sources to a reference current. The example current source selector assigns respective ones of the plurality of current sources to the digital bits in accordance with a bit-to-current source sequence selected to reduce current error in the analog output and changes the assignments based on the current source coupled to the calibrator.

Abstract translation: 公开了用于校准电流源中的误差消除的方法和装置。 在一个示例中，描述了将数字位转换为模拟输出信号的数模转换器，包括多个电流源，校准器和电流源选择器。 示例性电流源输出基本相同的电流，并且校准器被选择性地耦合以将电流源依次校准为参考电流。 示例性电流源选择器根据选择以减少模拟输出中的电流误差的位电流源序列将多个电流源中的相应电流源分配给数字位，并且基于耦合到 校准器

公开(公告)号：US20240156945A1

公开(公告)日：2024-05-16

申请号：US18282423

申请日：2022-03-17

Applicant: Joseph COTROPIA ,  Gaurav CHANDRA

Inventor： Joseph COTROPIA ,  Gaurav CHANDRA

IPC: A61K39/21 ,  A61K39/00 ,  C07K14/005 ,  C07K16/10 ,  C12Q1/70 ,  G01N33/569

CPC classification number: A61K39/21 ,  C07K14/005 ,  C07K16/1063 ,  C12Q1/703 ,  G01N33/56988 ,  A61K2039/505 ,  C12N2740/16034 ,  G01N2333/162

Abstract: Provided are highly conserved antigens and epitopes of HIV that can be used in vaccines and to produce bindings proteins (e.g., antibodies) for detecting, treating, preventing, or reducing the risk of HIV infection and the development of AIDS.