发明授权
- 专利标题: Pattern creation method, mask manufacturing method and semiconductor device manufacturing method
- 专利标题(中): 图案形成方法,掩模制造方法和半导体器件制造方法
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申请号: US12050764申请日: 2008-03-18
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公开(公告)号: US07669172B2公开(公告)日: 2010-02-23
- 发明人: Takeshi Ito , Satoshi Tanaka , Toshiya Kotani , Tadahito Fujisawa , Koji Hashimoto
- 申请人: Takeshi Ito , Satoshi Tanaka , Toshiya Kotani , Tadahito Fujisawa , Koji Hashimoto
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 代理机构: Finnegan, Henderson, Farabow Garrett & Dunner, L.L.P.
- 优先权: JP2007-071031 20070319
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being most proximate to the most extreme end pattern from the second layer and converting the extracted data to a third layer, generating data of a contacting pattern which contacts both the first most proximate pattern and the most extreme end pattern in a fourth layer, generating data of a non-overlapping pattern of the contacting pattern excluding overlapping portions with the most extreme end pattern and the first most proximate pattern in a fifth layer, extracting data of a second most proximate pattern being most proximate to the non-overlapping pattern and converting the extracted data to the first layer.
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