An integral plated semiconductor package substrate stiffener provides a low-cost and space-efficient mechanism for maintaining substrate planarity during the manufacturing process. By patterning and plating the stiffener along with the other substrate fabrication process steps, the difficulty of attaching a separate stiffener is averted. Also, the stiffener pattern can be provided around other substrate elements such as the circuit patterns and terminals, while maintaining requisite spacing. The stiffener is a two-layer metal structure, the first layer is a thin film metal layer on which a thicker outer metal layer is plated up. The two metal layers may be of different metals or alloys and the thin film metal layer may be the same layer plane that provides one of the substrate interconnect layers or may be the metal layer removed from other areas of the substrate during isolation of an embedded circuit layer.