公开(公告)号：US09129943B1

公开(公告)日：2015-09-08

申请号：US13434181

申请日：2012-03-29

申请人： Ronald Patrick Huemoeller ,  Michael Kelly ,  David Jon Hiner

发明人： Ronald Patrick Huemoeller ,  Michael Kelly ,  David Jon Hiner

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/04 ,  H01L21/44 ,  H01L21/768 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/3171 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/16265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/157 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/014

摘要： An array includes a substrate having a frontside surface and a backside surface. A backside cavity is formed in the backside surface. Backside through vias extend through the substrate from the frontside surface to the backside surface. Embedded component through vias extend through the substrate from the frontside surface to the backside cavity. An embedded component is mounted within the backside cavity and coupled to the embedded component through vias. In this manner, the embedded component is embedded within the substrate.

摘要翻译： 阵列包括具有前侧表面和背侧表面的基底。 背面空腔形成在背面。 背面穿过通孔从前侧表面延伸穿过基底到背面。 通过通孔的嵌入式部件从前侧表面延伸到背侧腔。 嵌入式组件安装在后侧空腔内，并通过通孔与嵌入式组件相连。 以这种方式，嵌入式部件嵌入在基板内。

公开(公告)号：US09048298B1

公开(公告)日：2015-06-02

申请号：US13434217

申请日：2012-03-29

申请人： Ronald Patrick Huemoeller ,  Michael Kelly ,  David Jon Hiner

发明人： Ronald Patrick Huemoeller ,  Michael Kelly ,  David Jon Hiner

IPC分类号： H01L23/42 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L21/44 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L21/76898 ,  H01L21/31 ,  H01L21/312 ,  H01L21/486 ,  H01L21/50 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/3675 ,  H01L23/48 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/03

摘要： Through vias extend through a substrate between a frontside surface and a backside surface, the through vias comprising active surface ends at the frontside surface. A frontside redistribution structure is coupled to the active surface ends, the frontside redistribution structure exerting force on the frontside surface, e.g., due to a difference in the thermal coefficient of expansion (TCE) between the frontside redistribution structure and the substrate. To prevent warpage of the substrate, a backside warpage control structure is coupled to the backside surface of the substrate. The backside warpage control structure exerts an equal but opposite force to the force exerted by the frontside redistribution structure thus avoiding warpage of the substrate.

摘要翻译： 穿过通孔在前侧表面和后侧表面之间延伸通过基底，通孔包括位于前侧表面的活性表面末端。 侧面再分布结构耦合到活动表面端，前侧再分布结构在前侧表面上施加力，例如由于前侧再分配结构和基底之间的热膨胀系数（TCE）的差异。 为了防止基板翘曲，背面翘曲控制结构耦合到基板的背面。 背面翘曲控制结构对由前侧再分布结构施加的力施加相等但相反的力，从而避免基底翘曲。

公开(公告)号：US09040349B2

公开(公告)日：2015-05-26

申请号：US13678046

申请日：2012-11-15

申请人： Michael G. Kelly ,  Ronald Patrick Huemoeller ,  Won Chul Do ,  David Jon Hiner

发明人： Michael G. Kelly ,  Ronald Patrick Huemoeller ,  Won Chul Do ,  David Jon Hiner

IPC分类号： H01L21/50

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/50 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L27/108 ,  H01L2221/68381 ,  H01L2224/13147 ,  H01L2224/29011 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/75704 ,  H01L2224/75744 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.

摘要翻译： 公开了具有管芯到插入件晶片第一接合的半导体器件封装的方法和系统，并且可以包括将包括电子器件的多个半导体管芯结合到插入器晶片，以及在管芯和插入器晶片之间施加底部填充材料。 可以应用模具材料来封装模具。 内插器晶片可以被薄化以暴露通过硅通孔（TSV），并且可以将金属触点施加到暴露的TSV。 内插器晶片可以被单个化以产生包括半导体管芯和插入器管芯的组件。 可以使用粘合剂膜将管芯放置在插入件晶片上。 可以使用激光切割工艺，反应离子蚀刻，锯切技术和等离子体蚀刻工艺中的一种或多种来切割插入器晶片。 可以使用质量回流或热压缩工艺将管芯结合到插入件晶片。

公开(公告)号：US08826531B1

公开(公告)日：2014-09-09

申请号：US11098995

申请日：2005-04-05

申请人： David Jon Hiner ,  Ronald Patrick Huemoeller ,  Sukianto Rusli

发明人： David Jon Hiner ,  Ronald Patrick Huemoeller ,  Sukianto Rusli

IPC分类号： H01R43/00 ,  H05K13/00

CPC分类号： H05K3/465 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2924/15311 ,  H05K3/0035 ,  H05K3/1216 ,  H05K3/18 ,  H05K2201/0195 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49169 ,  H01L2924/00014

摘要： A method for making an integrated circuit substrate having laminated laser-embedded circuit layers provides a multi-layer high-density mounting and interconnect structure for integrated circuits. A prepared substrate, which may be a rigid double-sided dielectric or film dielectric with conductive patterns plated, etched or printed on one or both sides is laminated with a thin-film dielectric on one or both sides. The thin-film is laser-ablated to form channels and via apertures and conductive material is plated or paste screened into the channels and apertures, forming a conductive interconnect pattern that is isolated by the channel sides and vias through to the conductive patterns on the prepared substrate. An integrated circuit die and external terminals can then be attached to the substrate, providing an integrated circuit having a high-density interconnect.

摘要翻译： 用于制造具有层叠的激光嵌入电路层的集成电路基板的方法为集成电路提供了多层高密度安装和互连结构。 制备的衬底，其可以是在一侧或两侧上镀有，蚀刻或印刷的导电图案的刚性双面电介质或膜电介质，其一面或两侧与薄膜电介质层压。 薄膜被激光烧蚀以形成通道并且通孔，并且导电材料被电镀或糊化物屏蔽到通道和孔中，形成通过通道侧和通孔隔离的导电互连图案到制备的导电图案 基质。 然后可以将集成电路管芯和外部端子连接到衬底，从而提供具有高密度互连的集成电路。

公开(公告)号：US08653674B1

公开(公告)日：2014-02-18

申请号：US13233606

申请日：2011-09-15

申请人： Robert Francis Darveaux ,  Brett Arnold Dunlap ,  Ronald Patrick Huemoeller

发明人： Robert Francis Darveaux ,  Brett Arnold Dunlap ,  Ronald Patrick Huemoeller

IPC分类号： H01L23/52

CPC分类号： H01L24/06 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/02371 ,  H01L2224/02379 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： A redistribution pattern is formed on active surfaces of electronic components while still in wafer form. The redistribution pattern routes bond pads of the electronic components to redistribution pattern terminals on the active surfaces of the electronic components. The bond pads are routed to the redistribution pattern terminals while still in wafer form, which is a low cost and high throughput process, i.e., very efficient process.

摘要翻译： 在电子元件的有源表面上仍然以晶片形式形成再分布图案。 再分配模式将电子部件的接合焊盘引导到电子部件的有效表面上的再分配模式端子。 接合焊盘被引导到再分布图案端子，同时仍然是晶片形式，这是低成本和高吞吐量的工艺，即非常有效的工艺。

公开(公告)号：US08426966B1

公开(公告)日：2013-04-23

申请号：US13569865

申请日：2012-08-08

申请人： Ronald Patrick Huemoeller ,  Rex Anderson ,  Ravi Kiran Chilukuri

发明人： Ronald Patrick Huemoeller ,  Rex Anderson ,  Ravi Kiran Chilukuri

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of fabricating a bumped chip package includes forming a first seed layer on a dielectric layer, the dielectric layer comprising a dielectric layer opening exposing a substrate terminal of a substrate, the first seed layer being formed within the dielectric layer opening and on the substrate terminal. A circuit pattern is plated on the first seed layer, wherein an exposed portion of the first seed layer is exposed from the circuit pattern. The exposed portion of the first seed layer is removed by laser-ablation. By using a laser-ablation process, a chemical etching process is avoided thus eliminating the need to treat or dispose of chemical etching hazardous waste. Further, circuit pattern width erosion and undercut of the circuit pattern associated with a chemical etching process are avoided.

摘要翻译： 制造凸起芯片封装的方法包括在电介质层上形成第一晶种层，所述电介质层包括暴露衬底的衬底端子的介质层开口，所述第一晶种层形成在所述电介质层开口内和所述衬底上 终奌站。 电路图案被电镀在第一种子层上，其中第一种子层的暴露部分从电路图案露出。 通过激光消融去除第一种子层的暴露部分。 通过使用激光烧蚀工艺，避免了化学蚀刻工艺，从而无需处理或处理化学腐蚀危险废物。 此外，避免了与化学蚀刻工艺相关联的电路图案宽度侵蚀和电路图案的底切。

公开(公告)号：US07923645B1

公开(公告)日：2011-04-12

申请号：US11765806

申请日：2007-06-20

申请人： Ronald Patrick Huemoeller ,  Sukianto Rusli ,  Robert F. Darveaux

发明人： Ronald Patrick Huemoeller ,  Sukianto Rusli ,  Robert F. Darveaux

IPC分类号： H05K1/03

CPC分类号： H05K3/428 ,  H01L2224/48091 ,  H05K1/185 ,  H05K3/205 ,  H05K3/421 ,  H05K3/4658 ,  H05K2201/0394 ,  H05K2201/10674 ,  H05K2203/0361 ,  H05K2203/0384 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2924/00014

摘要： A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.

摘要翻译： 第一图案化蚀刻停止层和第一图案化导体层通过电介质材料层压到第二图案化蚀刻停止层和第二图案化导体层。 由于与第一和第二图案化导体层的导体金属相比，第一和第二图案化蚀刻停止层的蚀刻停止金属是可选择的可蚀刻的，所以第一和第二图案化蚀刻停止层提供用于衬底形成蚀刻工艺的蚀刻停止。 以这种方式，避免了第一和第二图案化导体层的蚀刻，确保阻抗被控制在紧密公差内。

公开(公告)号：US07692286B1

公开(公告)日：2010-04-06

申请号：US12221797

申请日：2008-08-05

申请人： Ronald Patrick Huemoeller ,  Russ Lie ,  David Hiner

发明人： Ronald Patrick Huemoeller ,  Russ Lie ,  David Hiner

IPC分类号： H01L23/12

CPC分类号： H01L24/96 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/82

摘要： A method of forming an electronic component package includes: forming electrically conductive traces for connecting first selected bond pads of a plurality of bond pads on a first surface of an electronic component to corresponding bonding locations formed on a second surface of the electronic component; coupling the first surface of the electronic component to a first surface of a lower dielectric strip; coupling the second surface of the electronic component to a first surface of an upper dielectric strip; forming lower via apertures through the lower dielectric strip to expose second selected bond pads of the plurality of bond pads on the first surface of the electronic component; forming upper via apertures through the upper dielectric strip to expose the bonding locations on the second surface of the electronic component; filling the lower and upper via apertures with an electrically conductive material to form lower and upper vias electrically coupled to the first and second selected bond pads of the plurality of bond pads on the first surface of the electronic component.

摘要翻译： 形成电子部件封装的方法包括：形成导电迹线，用于将电子部件的第一表面上的多个接合焊盘的第一选定接合焊盘连接到形成在电子部件的第二表面上的相应接合位置; 将所述电子部件的第一表面耦合到下介电条的第一表面; 将所述电子部件的第二表面耦合到所述上介质条的第一表面; 通过所述下介电条形成下通孔，以暴露所述电子部件的第一表面上的多个接合焊盘的第二选定接合焊盘; 通过所述上介质条形成上通孔以暴露所述电子部件的第二表面上的接合位置; 用导电材料填充下通孔和上通孔，以形成电耦合到电子部件的第一表面上的多个接合焊盘的第一和第二选定接合焊盘的下通孔和上通孔。

公开(公告)号：US07145238B1

公开(公告)日：2006-12-05

申请号：US10839647

申请日：2004-05-05

申请人： Ronald Patrick Huemoeller ,  David Jon Hiner ,  Sukianto Rusli

发明人： Ronald Patrick Huemoeller ,  David Jon Hiner ,  Sukianto Rusli

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of the circuit pattern. Successive resist pattern applications and etching are used to form a via tier atop a circuit pattern that is connected by a thin plane of metal. After the tier is deposited, the thin metal plane is etched to isolate the circuit pattern elements. Dielectric is then deposited and the top half of the via is deposited over the tier. The tier may have a larger or smaller diameter with respect to the other half of the via, so that the via halves may be properly registered. Tin plating may also be used to control the etching process to provide etching control.

摘要翻译： 具有多层电镀通孔的半导体封装和衬底以低增量成本提供高密度盲孔解决方案。 通孔在电路图案的顶部被半镀，然后添加第二通孔半部以在隔离电路图案的元件之后完成通孔。 连续的抗蚀剂图案应用和蚀刻用于在通过金属薄层连接的电路图案之上形成通孔层。 在层沉积之后，蚀刻薄金属平面以隔离电路图案元件。 然后沉积介质，并将通孔的上半部分沉积在层上。 层可以具有相对于通孔的另一半具有更大或更小的直径，使得通孔半部可以被适当地登记。 也可以使用镀锡来控制蚀刻工艺以提供蚀刻控制。

公开(公告)号：US06967124B1

公开(公告)日：2005-11-22

申请号：US09884193

申请日：2001-06-19

申请人： Ronald Patrick Huemoeller ,  Sukianto Rusli

发明人： Ronald Patrick Huemoeller ,  Sukianto Rusli

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H05K1/05 ,  H05K1/18 ,  H05K3/06 ,  H05K3/10 ,  H05K3/44

CPC分类号： H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/4867 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/00014 ,  H05K1/056 ,  H05K1/182 ,  H05K3/062 ,  H05K3/107 ,  H05K3/445 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2203/0108 ,  H01L2224/05599

摘要： A die-attach method and assembly using film and epoxy bonds speeds manufacturing for large die assemblies while providing improved bond characteristics. An adhesive film defining an epoxy flow mask is attached to the die or substrate, epoxy is dispensed within the epoxy flow mask area and the die is then bonded to the substrate. The film controls the flow of the epoxy, preventing spillover. Additionally, the epoxy area can be made small with respect to the die size, reducing the time required to dispense the epoxy and reducing the amount of epoxy material required.

摘要翻译： 使用膜和环氧树脂粘合剂的芯片附接方法和组装加速了大型模具组件的制造，同时提供了改善的粘合特性。 将限定环氧流量掩模的粘合剂膜附着到模具或基底上，将环氧树脂分配在环氧树脂流动掩模区域内，然后将模具结合到基底上。 该胶片控制环氧树脂的流动，防止外溢。 此外，相对于模具尺寸，可以使环氧树脂面积较小，减少了分配环氧树脂所需的时间并减少了所需的环氧树脂材料的量。