发明授权
US07671413B2 SOI device with reduced junction capacitance 有权
具有降低结电容的SOI器件

SOI device with reduced junction capacitance
摘要:
An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.
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