A thin film transistor (TFT) array panel includes a substrate, a first signal line formed on the substrate, a gate insulating layer formed on the first signal line and having a first contact hole exposing a portion of the first signal line, a first semiconductor formed on the gate insulating layer, a second signal line formed on the first semiconductor and the gate insulating layer and a drain electrode formed on the first semiconductor and separated from the second signal line. The TFT array panel further includes a conductor formed on the gate insulating layer and connected to the first signal line through the first contact hole, a passivation layer formed on the second signal line, the drain electrode, and the conductor, and having a second contact hole exposing the drain electrode and a pixel electrode formed on the passivation layer and connected to the drain electrode through the second contact hole.