Invention Grant
- Patent Title: Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
- Patent Title (中): 使用低能量等离子体系制造高介电常数晶体管栅的方法和装置
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Application No.: US11614019Application Date: 2006-12-20
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Publication No.: US07678710B2Publication Date: 2010-03-16
- Inventor: Thai Cheng Chua , Steven Hung , Patricia M. Liu , Tatsuya Sato , Alex M. Paterson , Valentin Todorov , John P. Holland
- Applicant: Thai Cheng Chua , Steven Hung , Patricia M. Liu , Tatsuya Sato , Alex M. Paterson , Valentin Todorov , John P. Holland
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson & Sheridan, LLP
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/469

Abstract:
The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material. Embodiments of the invention also provide a cluster tool that is adapted to form a high-k dielectric material, terminate the surface of the high-k dielectric material, perform any desirable post treatment steps, and form the polysilicon and/or metal gate layers.
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