发明授权
- 专利标题： Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same
- 专利标题（中）： 具有多个DRAM存储单元的半导体器件及其制造方法
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申请号： US12213920申请日： 2008-06-26
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公开(公告)号： US07683419B2公开(公告)日： 2010-03-23
- 发明人: Satoru Akiyama , Takao Watanabe , Yuichi Matsui , Masahiko Hiratani
- 申请人： Satoru Akiyama , Takao Watanabe , Yuichi Matsui , Masahiko Hiratani
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Mattingly & Malur, P.C.
- 主分类号： H01L29/78
- IPC分类号： H01L29/78
摘要：
A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.
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