发明授权
- 专利标题: PLL circuit
- 专利标题(中): PLL电路
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申请号: US10585779申请日: 2004-12-29
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公开(公告)号: US07683721B2公开(公告)日: 2010-03-23
- 发明人: Johannes Petrus Maria Van Lammeren , Jozef Jacobus Agnes Maria Verlinden , Edwin Jan Schapendonk
- 申请人: Johannes Petrus Maria Van Lammeren , Jozef Jacobus Agnes Maria Verlinden , Edwin Jan Schapendonk
- 申请人地址: NL Eindhoven
- 专利权人: NXP B.V.
- 当前专利权人: NXP B.V.
- 当前专利权人地址: NL Eindhoven
- 优先权: EP04100072 20040112
- 国际申请: PCT/IB2004/052931 WO 20041229
- 国际公布: WO2005/069489 WO 20050728
- 主分类号: H03L7/00
- IPC分类号: H03L7/00
摘要:
The present invention relates to a phase locked loop arrangement having an oscillator circuit (240) controlled in response to an output signal of a phase or frequency detection circuit (210), wherein change control (130) are provided for generating a blocking signal in response to the outputs of a first timer (110) to which a predetermined threshold frequency is supplied and a second timer (112) to which an output frequency of the oscillator circuit (240) is supplied. Based on the blocking signal, blocking (260) suppress supply of the output signal to said oscillator circuit (240). Thereby, the output frequency of the PLL arrangement can be prevented from changing beyond the frequency threshold, while only one PLL circuit is required.
公开/授权文献
- US20090189698A1 Pll circuit 公开/授权日:2009-07-30
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