发明授权
US07687303B1 Method for determining via/contact pattern density effect in via/contact etch rate
有权
确定通孔/接触蚀刻速率的通孔/接触图案密度效应的方法
- 专利标题: Method for determining via/contact pattern density effect in via/contact etch rate
- 专利标题(中): 确定通孔/接触蚀刻速率的通孔/接触图案密度效应的方法
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申请号: US11264930申请日: 2005-11-01
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公开(公告)号: US07687303B1公开(公告)日: 2010-03-30
- 发明人: Valeriy Sukharev , Ara Markosian
- 申请人: Valeriy Sukharev , Ara Markosian
- 申请人地址: US OR Wilsonville
- 专利权人: Mentor Graphics Corporation
- 当前专利权人: Mentor Graphics Corporation
- 当前专利权人地址: US OR Wilsonville
- 主分类号: H01L21/44
- IPC分类号: H01L21/44
摘要:
A method for determining an effect of via/contact pattern density in via/contact etch rate of a wafer includes determining a neutral etchant species number flux intersecting each via/contact mouth as a function of local layout characteristics and determining variations in the neutral etchant species flux number as a function of the via/contact pattern density in a wafer scale. The comparison of these number fluxes provides the capability to discriminate an underetched or an overetched via/contact from normal vias/contacts satisfying an etch tolerance criterion. Chip designers can modify the layout design to minimize via/contact failures. Chip manufacturers can modify the etching process to minimize via/contact failures.
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