发明授权
US07687369B2 Method of forming fine metal patterns for a semiconductor device using a damascene process
有权
使用镶嵌工艺形成用于半导体器件的精细金属图案的方法
- 专利标题: Method of forming fine metal patterns for a semiconductor device using a damascene process
- 专利标题(中): 使用镶嵌工艺形成用于半导体器件的精细金属图案的方法
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申请号: US11896512申请日: 2007-09-04
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公开(公告)号: US07687369B2公开(公告)日: 2010-03-30
- 发明人: Cha-won Koh , Jeong-lim Nam , Gi-sung Yeo , Sang-jin Kim , Sung-gon Jung
- 申请人: Cha-won Koh , Jeong-lim Nam , Gi-sung Yeo , Sang-jin Kim , Sung-gon Jung
- 申请人地址: KR Suwon-si, Gyeonggi-do
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si, Gyeonggi-do
- 代理机构: Lee & Morse, P.C.
- 优先权: KR10-2007-0016797 20070216
- 主分类号: H01L21/76
- IPC分类号: H01L21/76
摘要:
A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.
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