公开(公告)号：US07687369B2

公开(公告)日：2010-03-30

申请号：US11896512

申请日：2007-09-04

申请人： Cha-won Koh ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Sang-jin Kim ,  Sung-gon Jung

发明人： Cha-won Koh ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Sang-jin Kim ,  Sung-gon Jung

IPC分类号： H01L21/76

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32115 ,  H01L21/32134

摘要： A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.

摘要翻译： 一种形成精细金属互连图案的方法包括在基板上形成绝缘膜，在绝缘膜上形成多个模具图案，其间具有第一间隔，使得模具图案具有第一布局，在第一空间中形成金属硬掩模图案 通过镶嵌工艺去除模具图案，通过金属硬掩模图案蚀刻绝缘膜以形成具有第二间隔的绝缘膜图案，第二空间具有第一布局，并且在第二空间中形成具有第一布局的金属互连图案 通过大马士革的过程。

公开(公告)号：US20080200026A1

公开(公告)日：2008-08-21

申请号：US11896512

申请日：2007-09-04

申请人： Cha-won Koh ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Sang-jin Kim ,  Sung-gon Jung

发明人： Cha-won Koh ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Sang-jin Kim ,  Sung-gon Jung

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32115 ,  H01L21/32134

摘要： A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.

摘要翻译： 一种形成精细金属互连图案的方法包括在基板上形成绝缘膜，在绝缘膜上形成多个模具图案，其间具有第一间隔，使得模具图案具有第一布局，在第一空间中形成金属硬掩模图案 通过镶嵌工艺去除模具图案，通过金属硬掩模图案蚀刻绝缘膜以形成具有第二间隔的绝缘膜图案，第二空间具有第一布局，并且在第二空间中形成具有第一布局的金属互连图案 通过大马士革的过程。

公开(公告)号：US08278221B2

公开(公告)日：2012-10-02

申请号：US13181655

申请日：2011-07-13

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/331

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US08003543B2

公开(公告)日：2011-08-23

申请号：US12759771

申请日：2010-04-14

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US20080090419A1

公开(公告)日：2008-04-17

申请号：US11727124

申请日：2007-03-23

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US20110269294A1

公开(公告)日：2011-11-03

申请号：US13181655

申请日：2011-07-13

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/762

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US20100197139A1

公开(公告)日：2010-08-05

申请号：US12759771

申请日：2010-04-14

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US07732341B2

公开(公告)日：2010-06-08

申请号：US11727124

申请日：2007-03-23

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US20070181828A1

公开(公告)日：2007-08-09

申请号：US11656467

申请日：2007-01-23

申请人： Je-bum Yoon ,  Cha-won Koh ,  Myoung-ho Jung ,  Gi-sung Yeo ,  Sang-jin Kim

发明人： Je-bum Yoon ,  Cha-won Koh ,  Myoung-ho Jung ,  Gi-sung Yeo ,  Sang-jin Kim

IPC分类号： G21G5/00

CPC分类号： H01J37/3177 ,  B82Y10/00 ,  B82Y40/00 ,  H01J2237/201 ,  H01J2237/31774

摘要： Disclosed is an E-beam lithography system for synchronously irradiating surfaces of a plurality of substrates. The E-beam lithography system may include a loading unit loading and unloading substrates, an alignment chamber aligning the substrates, a transfer chamber transferring the substrates from the loading unit or chambers, a lithography chamber radiating one or more electron beams onto the substrates, and a vacuum chamber creating a vacuum in the chambers. A stage may be installed in the lithography chamber such that the substrates may be mounted on the stage and radiated with one or more electron beams.

摘要翻译： 公开了一种用于同时照射多个基板的表面的电子束光刻系统。 电子束光刻系统可以包括加载单元装载和卸载基板，对准基板的对准室，从加载单元或室转移基板的传送室，将一个或多个电子束辐射到基板上的光刻室，以及 在室中产生真空的真空室。 平台可以安装在光刻室中，使得基板可以安装在平台上并用一个或多个电子束辐射。

公开(公告)号：US07723702B2

公开(公告)日：2010-05-25

申请号：US11656467

申请日：2007-01-23

申请人： Je-bum Yoon ,  Cha-won Koh ,  Myoung-ho Jung ,  Gi-sung Yeo ,  Sang-jin Kim

发明人： Je-bum Yoon ,  Cha-won Koh ,  Myoung-ho Jung ,  Gi-sung Yeo ,  Sang-jin Kim

IPC分类号： G21G5/00

CPC分类号： H01J37/3177 ,  B82Y10/00 ,  B82Y40/00 ,  H01J2237/201 ,  H01J2237/31774

摘要： Disclosed is an E-beam lithography system for synchronously irradiating surfaces of a plurality of substrates. The E-beam lithography system may include a loading unit loading and unloading substrates, an alignment chamber aligning the substrates, a transfer chamber transferring the substrates from the loading unit or chambers, a lithography chamber radiating one or more electron beams onto the substrates, and a vacuum chamber creating a vacuum in the chambers. A stage may be installed in the lithography chamber such that the substrates may be mounted on the stage and radiated with one or more electron beams.

摘要翻译： 公开了一种用于同时照射多个基板的表面的电子束光刻系统。 电子束光刻系统可以包括加载单元装载和卸载基板，对准基板的对准室，从加载单元或室转移基板的传送室，将一个或多个电子束辐射到基板上的光刻室，以及 在室中产生真空的真空室。 平台可以安装在光刻室中，使得基板可以安装在平台上并用一个或多个电子束辐射。