Invention Grant
US07687369B2 Method of forming fine metal patterns for a semiconductor device using a damascene process
有权
使用镶嵌工艺形成用于半导体器件的精细金属图案的方法
- Patent Title: Method of forming fine metal patterns for a semiconductor device using a damascene process
- Patent Title (中): 使用镶嵌工艺形成用于半导体器件的精细金属图案的方法
-
Application No.: US11896512Application Date: 2007-09-04
-
Publication No.: US07687369B2Publication Date: 2010-03-30
- Inventor: Cha-won Koh , Jeong-lim Nam , Gi-sung Yeo , Sang-jin Kim , Sung-gon Jung
- Applicant: Cha-won Koh , Jeong-lim Nam , Gi-sung Yeo , Sang-jin Kim , Sung-gon Jung
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Lee & Morse, P.C.
- Priority: KR10-2007-0016797 20070216
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.
Public/Granted literature
- US20080200026A1 Method of forming fine metal patterns for a semiconductor device using a damascene process Public/Granted day:2008-08-21
Information query
IPC分类: