Invention Grant
US07687394B2 Method for forming inter-layer dielectric of low dielectric constant and method for forming copper wiring using the same
失效
用于形成低介电常数的层间电介质的方法及使用其形成铜布线的方法
- Patent Title: Method for forming inter-layer dielectric of low dielectric constant and method for forming copper wiring using the same
- Patent Title (中): 用于形成低介电常数的层间电介质的方法及使用其形成铜布线的方法
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Application No.: US11604920Application Date: 2006-11-27
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Publication No.: US07687394B2Publication Date: 2010-03-30
- Inventor: Jae Suk Lee
- Applicant: Jae Suk Lee
- Applicant Address: KR Seoul
- Assignee: Dongbu Electronics Co., Ltd.
- Current Assignee: Dongbu Electronics Co., Ltd.
- Current Assignee Address: KR Seoul
- Agency: The Law Offices of Andrew D. Fortney
- Agent Andrew D. Fortney
- Priority: KR10-2005-0117573 20051205
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A method for forming a dielectric layer having a low dielectric constant and a method for forming copper wiring using the same are provided. In the method for forming a dielectric, an etch stop layer and a first dielectric are sequentially formed on a semiconductor substrate. Next, the first dielectric is selectively etched to form a pattern, and a second dielectric is formed thereon. Here, the second dielectric may be formed using a plasma enhanced chemical deposition method to have pores or voids therein. Then, the dielectric is planarized and a damascene copper wiring is formed. Since the dielectric includes pores or voids, it may have a very low dielectric constant, which results in an improvement in RC delay.
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