A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the first control signal. Based on the pulse width of the pulse signal, it is determined whether a timing margin between activation of the first control signal and activation of the second control signal is within a predetermined range, and the timing margin is adjusted responsive to the determination. For example, the pulse signal may be a timing measurement signal including a first pulse signal representing a first timing margin between a word line enable signal and a bit line sensing enable signal, a second pulse signal representing a second timing margin between a column select line enable signal and a first read pulse signal, and a third pulse signal representing a third timing margin between a word line disable signal and a bit line equalizing signal. Related devices are also discussed.