Invention Grant
- Patent Title: Open-drain output circuit
- Patent Title (中): 开漏输出电路
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Application No.: US11710941Application Date: 2007-02-27
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Publication No.: US07692451B2Publication Date: 2010-04-06
- Inventor: Toru Ishikawa
- Applicant: Toru Ishikawa
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Foley & Lardner LLP
- Priority: JP2006-054707 20060301
- Main IPC: H03K19/094
- IPC: H03K19/094

Abstract:
A pulse generation section generates a pulse which is at H-level for the predetermined period of time from the timing of the input signal DATA changing to L-level. A main output section outputs a signal of L-level with transistors P1, N1, and N2 turned ON, while the pulse generation section outputs a pulse. When the pulse falls, the transistors P1 and N1 are turned OFF, and a potential of an output node is held at L-level by resistors of a L-level holding section.
Public/Granted literature
- US20070205806A1 Open-drain output circuit Public/Granted day:2007-09-06
Information query
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