发明授权
- 专利标题： Automated design process and method for multi-rail cells and connections
- 专利标题（中）： 多轨电池和连接的自动设计过程和方法
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申请号： US11313969申请日： 2005-12-20
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公开(公告)号： US07694241B1公开(公告)日： 2010-04-06
- 发明人: Srikanth Jadcherla , Sriram Kotni
- 申请人： Srikanth Jadcherla , Sriram Kotni
- 申请人地址： US CA Mountain View
- 专利权人： Synopsys, Inc.
- 当前专利权人： Synopsys, Inc.
- 当前专利权人地址： US CA Mountain View
- 代理机构： Park, Vaughan & Fleming LLP
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
Automated design process and method with set of syntactic elements compensates for inability to represent voltage island connection of multi-rail cells in RTL source files in traditional design process which inhibits development of design automation methods and causes hardship and risk of failure to simulate, synthesize, perform physical design or formally verify a semiconductor chip design implemented with multi-rail.
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