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公开(公告)号：US08255859B2
公开(公告)日：2012-08-28
申请号：US12467955
申请日：2009-05-18
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
摘要翻译： 多电压电路设计验证将设计元件分为等电压轨块。 获得有关等电压轨块之间交叉连接的信息。 在电路设计中模拟电压效应，并根据交叉信息，对仿真结果进行了修改。 这为多电压电路设计产生更准确的模拟结果。
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2.发明授权公开(公告)号：US07694252B1
公开(公告)日：2010-04-06
申请号：US11738483
申请日：2007-04-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Verification of a design for a multi-voltage circuit which defines a plurality of iso-voltage rail blocks, and which comprises voltage state information for the iso-voltage-rail blocks. Verification includes generating cross-over information regarding a cross-over signal between two iso-voltage-rail blocks, identifying the voltage state relationship between the two iso-voltage-rail blocks based on the voltage state information, and verifying the validity of the cross-over signal based on the determined voltage state relationship.
摘要翻译： 验证限定多个等电压轨道块的多电压电路的设计，并且其包括用于等电压轨道块的电压状态信息。 验证包括产生关于两个等电压轨块之间的交叉信号的交叉信息，基于电压状态信息识别两个等电压轨块之间的电压状态关系，以及验证交叉的有效性 基于确定的电压状态关系的-over信号。
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公开(公告)号：US20080250364A1
公开(公告)日：2008-10-09
申请号：US11696724
申请日：2007-04-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
摘要翻译： 多电压电路设计验证将设计元件分为等电压轨块。 获得有关等电压轨块之间交叉连接的信息。 在电路设计中模拟电压效应，并根据交叉信息，对仿真结果进行了修改。 这为多电压电路设计产生更准确的模拟结果。
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4.发明授权公开(公告)号：US07694241B1
公开(公告)日：2010-04-06
申请号：US11313969
申请日：2005-12-20
申请人： Srikanth Jadcherla , Sriram Kotni
发明人： Srikanth Jadcherla , Sriram Kotni
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Automated design process and method with set of syntactic elements compensates for inability to represent voltage island connection of multi-rail cells in RTL source files in traditional design process which inhibits development of design automation methods and causes hardship and risk of failure to simulate, synthesize, perform physical design or formally verify a semiconductor chip design implemented with multi-rail.
摘要翻译： 自动化设计过程和方法与传统设计过程中的语法元素集合补偿了无法代表RTL源文件中多轨电池的电压岛连接，阻碍了设计自动化方法的开发，造成了难以模拟，综合， 执行物理设计或正式验证利用多轨实现的半导体芯片设计。
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公开(公告)号：US20090228852A1
公开(公告)日：2009-09-10
申请号：US12467955
申请日：2009-05-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
摘要翻译： 多电压电路设计验证将设计元件分为等电压轨块。 获得有关等电压轨块之间交叉连接的信息。 在电路设计中模拟电压效应，并根据交叉信息，对仿真结果进行了修改。 这为多电压电路设计产生更准确的模拟结果。
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公开(公告)号：US07546566B2
公开(公告)日：2009-06-09
申请号：US11696724
申请日：2007-04-05
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
摘要翻译： 多电压电路设计验证将设计元件分为等电压轨块。 获得有关等电压轨块之间交叉连接的信息。 在电路设计中模拟电压效应，并根据交叉信息，对仿真结果进行了修改。 这为多电压电路设计产生更准确的模拟结果。
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