A semiconductor memory device is capable of simultaneously carrying out a first operation and a second operation. The semiconductor memory device includes first and second control circuits, a select control circuit, and a select circuit. The first control circuit controls the first operation according to a first address signal and outputs a read start signal when the reading of the data is started. The second control circuit controls the second operation according to a second address signal and outputs a sequence flag when the first and second addresses coincide with each other. The select control circuit generates a select control signal. The select control signal is asserted if the second operation is carried out. The first control circuit instructs the select circuit to select the sequence flag if the select control signal is asserted or the data if the select control signal is negated.