公开(公告)号：US07791967B2

公开(公告)日：2010-09-07

申请号：US11837722

申请日：2007-08-13

Applicant: Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara

Inventor： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara

IPC: G11C29/12

CPC classification number: G11C29/14 ,  G11C16/04

Abstract: A semiconductor memory device includes a semiconductor memory, an auto-operation control circuit which outputs a clock signal, a sync read control circuit which outputs a sync read address in sync with the clock signal, a read control circuit which selects a read address of the semiconductor memory in accordance with an address of the sync read address, a read sense amplifier circuit which outputs a data read signal that is produced by sensing data that is read out of the semiconductor memory in accordance with the read address, and a determination circuit which compares the data read signal with an expectation value.

Abstract translation: 半导体存储器件包括半导体存储器，输出时钟信号的自动操作控制电路，与时钟信号同步地输出同步读取地址的同步读取控制电路，选择读取地址的读取控制电路 半导体存储器，根据同步读取地址的地址，读出读出放大器电路，其输出通过根据读取的地址感测从半导体存储器读出的数据而产生的数据读取信号;以及确定电路， 将数据读取信号与期望值进行比较。

公开(公告)号：US20080282119A1

公开(公告)日：2008-11-13

申请号：US11877188

申请日：2007-10-23

Applicant: Takahiro Suzuki ,  Shinya Fujisawa ,  Shoichiro Hashimoto ,  Tokumasa Hara

Inventor： Takahiro Suzuki ,  Shinya Fujisawa ,  Shoichiro Hashimoto ,  Tokumasa Hara

IPC: G11C29/12 ,  G06F11/27

CPC classification number: G11C29/16

Abstract: A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory.

Abstract translation: 一种存储装置，包括存储步骤项目的非易失性存储器，参数起始地址和具有与参数起始地址对应的地址并定义步骤项目的参数的参数，以及控制器，其在非易失性存储器上执行 测试步骤对应于由参数定义的步骤项目，控制器形成在与非易失性存储器相同的芯片中。

公开(公告)号：US08885185B2

公开(公告)日：2014-11-11

申请号：US13582771

申请日：2011-02-03

Applicant: Shinya Fujisawa ,  Kiyoshi Takagi ,  Takenori Kitada ,  Hitoshi Koyanagi

Inventor： Shinya Fujisawa ,  Kiyoshi Takagi ,  Takenori Kitada ,  Hitoshi Koyanagi

IPC: G06F3/12 ,  H04N1/00 ,  G03G15/00 ,  G06K15/02 ,  G03G21/14 ,  H04N1/413

CPC classification number: G03G21/14 ,  G03G15/502 ,  G06F3/1297 ,  G06K15/1849 ,  G06K15/1865 ,  H04N1/00127 ,  H04N1/413 ,  H04N2201/0094

Abstract: An image forming system comprising: a controller, provided with a list creation means to create a display list by analyzing PDL data, a decompression means to decompress compressed image data, a drawing means to execute drawing based on the image data, and a print data creation means to create the print data based on the image data, for sending the print data to a printer; and a rasterization accelerator, provided with a second drawing means to execute drawing processing based on the display list, and a compression means to compress the image data drawn by the second drawing unit, for sending the image data to the controller, wherein the rasterization accelerator comprises a determination means for determining, based on the information of the display list, whether to execute or not the compression of the image data, and a compression method in case of executing the compression.

Abstract translation: 一种图像形成系统，包括：控制器，设置有通过分析PDL数据来创建显示列表的列表创建装置，用于解压缩压缩图像数据的解压缩装置，基于图像数据执行绘图的绘图装置和打印数据 创建装置，用于基于图像数据创建打印数据，用于将打印数据发送到打印机; 以及光栅化加速器，具有：第二绘制单元，其基于所述显示列表执行绘图处理;以及压缩单元，压缩由所述第二绘图单元绘制的图像数据，将所述图像数据发送到所述控制器，其中所述光栅化加速器 包括确定装置，用于基于显示列表的信息确定是否执行图像数据的压缩，以及在执行压缩的情况下确定压缩方法。

公开(公告)号：US20130027735A1

公开(公告)日：2013-01-31

申请号：US13637939

申请日：2011-01-24

Applicant: Takenori Kitada, I ,  Kiyoshi Takagi ,  Hitoshi Koyanagi ,  Shinya Fujisawa

Inventor： Takenori Kitada, I ,  Kiyoshi Takagi ,  Hitoshi Koyanagi ,  Shinya Fujisawa

IPC: G06F3/12

CPC classification number: G06K15/1857 ,  G06K15/1888 ,  G06T1/20

Abstract: Disclosed is an image forming apparatus that makes it possible to suppress the scale enlargement of the electric circuit, so as to make the apparatus highly flexible. The apparatus forms an image based on image data acquired by applying a rendering operation to depiction commands and includes: a converting section to convert input data to the depiction commands; a first rendering section to apply the rendering operation to a first depiction command; a second rendering section to apply the rendering operation to a second depiction command; a reading section to read out first information from the storage section; a determining section to determine whether the first rendering section or the second rendering section should apply the rendering operation to each of the depiction commands; and a control, section to make either the first rendering section or the second rendering section apply the rendering operation to each of the depiction commands.

Abstract translation: 公开了一种能够抑制电路的规模扩大的图像形成装置，从而使装置高度灵活。 该装置基于通过对描绘命令应用呈现操作获取的图像数据形成图像，并且包括：转换部分，用于将输入数据转换成描绘命令; 第一渲染部分，用于将呈现操作应用于第一描绘命令; 第二渲染部分，用于将呈现操作应用于第二描绘命令; 读取部，从存储部读出第一信息; 确定部分，用于确定第一渲染部分或第二渲染部分是否应该对每个描绘命令应用渲染操作; 以及使第一渲染部分或第二渲染部分的控制部分将呈现操作应用于每个描绘命令。

公开(公告)号：US20130003101A1

公开(公告)日：2013-01-03

申请号：US13582771

申请日：2011-02-03

Applicant: Shinya Fujisawa ,  Kiyoshi Takagi ,  Takenori Kitada ,  Hitoshi Koyanagi

Inventor： Shinya Fujisawa ,  Kiyoshi Takagi ,  Takenori Kitada ,  Hitoshi Koyanagi

IPC: G06K15/02

CPC classification number: G03G21/14 ,  G03G15/502 ,  G06F3/1297 ,  G06K15/1849 ,  G06K15/1865 ,  H04N1/00127 ,  H04N1/413 ,  H04N2201/0094

Abstract: An image forming system comprising: a controller, provided with a list creation means to create a display list by analyzing PDL data decompression means to decompress compressed image data, a drawing means to execute drawing based on the image data, and a print data creation means to create the print data based on the image data for sending the print data to a printer; and a rasterization accelerator, provided with a second drawing means to execute drawing processing based on the display list, and a compression means to compress the image data drawn by the second drawing unit, for sending the image data to the controller, wherein the rasterization accelerator comprises determination means for determining, based on the information of the display list, whether to execute or not the compression of the image data, and a compression method in case of executing the compression.

Abstract translation: 一种图像形成系统，包括：控制器，其具有通过分析PDL数据解压缩装置来解压缩压缩图像数据来创建显示列表的列表创建装置，基于图像数据执行绘图的绘制装置，以及打印数据创建装置 基于用于将打印数据发送到打印机的图像数据来创建打印数据; 以及光栅化加速器，具有：第二绘制单元，其基于所述显示列表执行绘图处理;以及压缩单元，压缩由所述第二绘图单元绘制的图像数据，将所述图像数据发送到所述控制器，其中所述光栅化加速器 包括确定装置，用于基于显示列表的信息确定是否执行图像数据的压缩，以及在执行压缩的情况下确定压缩方法。

公开(公告)号：US20120246422A1

公开(公告)日：2012-09-27

申请号：US13492119

申请日：2012-06-08

Applicant: Takahiro SUZUKI ,  Shinya FUJISAWA ,  Tokumasa HARA ,  Masuji NISHIYAMA

Inventor： Takahiro SUZUKI ,  Shinya FUJISAWA ,  Tokumasa HARA ,  Masuji NISHIYAMA

IPC: G06F12/00

CPC classification number: G11C16/06

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

公开(公告)号：US08219744B2

公开(公告)日：2012-07-10

申请号：US13301969

申请日：2011-11-22

Applicant: Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

Inventor： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

IPC: G06F12/02

CPC classification number: G11C16/06

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract translation: 半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。 存储单元阵列包括非易失性存储单元。 电源电路包括第一寄存器并产生电压。 读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。 控制电路包括第三寄存器并控制电源电路和读出放大器的操作。 处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。 控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

公开(公告)号：US20120063229A1

公开(公告)日：2012-03-15

申请号：US13301969

申请日：2011-11-22

Applicant: Takahiro SUZUKI ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

Inventor： Takahiro SUZUKI ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

IPC: G11C16/26

CPC classification number: G11C16/06

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract translation: 半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。 存储单元阵列包括非易失性存储单元。 电源电路包括第一寄存器并产生电压。 读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。 控制电路包括第三寄存器并控制电源电路和读出放大器的操作。 处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。 控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

公开(公告)号：US20080181022A1

公开(公告)日：2008-07-31

申请号：US12019245

申请日：2008-01-24

Applicant: Shinya Fujisawa ,  Tokumasa Hara ,  Takahiro Suzuki

Inventor： Shinya Fujisawa ,  Tokumasa Hara ,  Takahiro Suzuki

IPC: G11C7/22

CPC classification number: G11C7/1045 ,  G11C7/22 ,  G11C16/26 ,  G11C2216/22

Abstract: A semiconductor memory device is capable of simultaneously carrying out a first operation and a second operation. The semiconductor memory device includes first and second control circuits, a select control circuit, and a select circuit. The first control circuit controls the first operation according to a first address signal and outputs a read start signal when the reading of the data is started. The second control circuit controls the second operation according to a second address signal and outputs a sequence flag when the first and second addresses coincide with each other. The select control circuit generates a select control signal. The select control signal is asserted if the second operation is carried out. The first control circuit instructs the select circuit to select the sequence flag if the select control signal is asserted or the data if the select control signal is negated.

Abstract translation: 半导体存储器件能够同时执行第一操作和第二操作。 半导体存储器件包括第一和第二控制电路，选择控制电路和选择电路。 第一控制电路根据第一地址信号控制第一操作，并且当数据读取开始时输出读取开始信号。 第二控制电路根据第二地址信号控制第二操作，并且当第一和第二地址彼此一致时输出序列标志。 选择控制电路产生选择控制信号。 如果执行第二操作，则选择控制信号被置位。 如果选择控制信号被断言，则第一控制电路指示选择电路选择序列标志，或者如果选择控制信号被否定则指示数据。

公开(公告)号：US20080177928A1

公开(公告)日：2008-07-24

申请号：US12018493

申请日：2008-01-23

Applicant: Takahiro SUZUKI ,  Shinya FUJISAWA ,  Tokumasa HARA ,  Masuji NISHIYAMA

Inventor： Takahiro SUZUKI ,  Shinya FUJISAWA ,  Tokumasa HARA ,  Masuji NISHIYAMA

IPC: G06F12/00

CPC classification number: G11C16/06

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract translation: 半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。 存储单元阵列包括非易失性存储单元。 电源电路包括第一寄存器并产生电压。 读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。 控制电路包括第三寄存器并控制电源电路和读出放大器的操作。 处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。 控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。