发明授权
US07707354B2 SRAM cache and flash micro-controller with differential packet interface
失效
具有差分数据包接口的SRAM缓存和闪存微控制器
- 专利标题: SRAM cache and flash micro-controller with differential packet interface
- 专利标题(中): 具有差分数据包接口的SRAM缓存和闪存微控制器
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申请号: US11876251申请日: 2007-10-22
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公开(公告)号: US07707354B2公开(公告)日: 2010-04-27
- 发明人: Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
- 申请人: Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
- 申请人地址: US CA San Jose
- 专利权人: Super Talent Electronics, Inc.
- 当前专利权人: Super Talent Electronics, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: gPatent LLC
- 代理商 Stuart T. Auvinen
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.