公开(公告)号：US08959280B2

公开(公告)日：2015-02-17

申请号：US13540569

申请日：2012-07-02

申请人： Frank Yu ,  Abraham C. Ma ,  Shimon Chen

发明人： Frank Yu ,  Abraham C. Ma ,  Shimon Chen

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G06F3/06 ,  G06F12/08 ,  G11C14/00 ,  G11C11/56 ,  G11C13/00 ,  G11C29/00

CPC分类号： G06F12/0246 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0688 ,  G06F12/0868 ,  G06F2212/401 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C11/5678 ,  G11C13/0004 ,  G11C14/0018 ,  G11C29/765

摘要： A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

摘要翻译： 闪存驱动器通过减少对闪存的写入来提高耐用性和使用寿命。 耐久性翻译层（ETL）在DRAM缓冲区中创建，并提供临时存储以减少闪存磨损。 智能存储交换机（SSS）控制器将主机访问分类为内存管理，临时文件，文件分配表（FAT）和文件描述符块（FDB）条目所使用的页面文件以及用户数据文件时，分配数据类型位，使用地址 从FAT读取的范围和文件扩展名。 分页文件和临时文件不会写入闪存。 部分页面数据由通过统一映射表指向的子扇区映射表进行打包和扇区映射，统一映射表将数据类型位和指针存储到DRAM中的数据或表。 部分行业包装在一起，以减少DRAM的使用和闪存磨损。 DRAM中的备用/交换区域可减少闪存磨损。 当纠错失败时，调整参考电压。

公开(公告)号：US08341332B2

公开(公告)日：2012-12-25

申请号：US12186471

申请日：2008-08-05

申请人： Abraham C. Ma ,  David Q. Chow ,  Charles C. Lee ,  Frank Yu

发明人： Abraham C. Ma ,  David Q. Chow ,  Charles C. Lee ,  Frank Yu

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0246 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0664 ,  G06F3/0688 ,  G06F2212/7201 ,  G06F2212/7208 ,  G06F2212/7211 ,  G11C13/0004

摘要： A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.

摘要翻译： 固态磁盘（SSD）具有智能存储交换机，智能存储交易管理器重新命令用于访问下游单芯片闪存设备的主机命令。 每个单芯片闪存设备具有将逻辑块地址（LBA）转换为访问单芯片闪存设备中的闪存块的物理块地址（PBA）的较低级别的控制器。 磨损均衡和坏块重映射由每个单芯片闪存设备执行，并且在智能存储交换机中的虚拟存储处理器处于更高级别。 智能存储事务管理器和单芯片闪存设备之间的虚拟存储网桥将LBA总线上的LBA交易桥接到单芯片闪存设备。 单芯片闪速存储器件的多个通道之间的数据条带化和交错由智能存储事务管理器控制在高电平，而可以在每个单芯片闪速存储器件内执行进一步的交错和重新映射。

公开(公告)号：US08304871B2

公开(公告)日：2012-11-06

申请号：US13080320

申请日：2011-04-05

申请人： Frank Yu ,  Lance Wright ,  Chien-Te Feng ,  Sandra Horton

发明人： Frank Yu ,  Lance Wright ,  Chien-Te Feng ,  Sandra Horton

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/30519 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/1305 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A packaged semiconductor device includes a semiconductor die including a substrate having a topside including active circuitry and a bottomside with at least one backside metal layer directly attached. A package including a molding material having a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The topside of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the backside metal layer along a bottom surface of the package. Bond wires couple pads on the topside of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the backside metal layer are all substantially planar to one another.

摘要翻译： 封装的半导体器件包括半导体管芯，该半导体管芯包括具有包括有源电路的顶面的基板和具有直接附接的至少一个背侧金属层的底部底部。 包括具有管芯焊盘和多个引线的成型材料的封装被封装在模制材料内，其中引线包括包括结合部分的暴露部分。 半导体管芯的顶侧附接到管芯焊盘，并且封装件包括沿着封装的底表面暴露背面金属层的间隙。 键合线将半导体芯片顶端的引线耦合到引线。 接合部分，沿着封装的底表面的成型材料和背面金属层彼此基本上是平面的。

公开(公告)号：US08296467B2

公开(公告)日：2012-10-23

申请号：US12947211

申请日：2010-11-16

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma ,  Shimon Chen

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma ,  Shimon Chen

IPC分类号： G06F3/00 ,  G06F12/00

CPC分类号： G06F9/4401 ,  G06F13/387 ,  G06F2213/3854

摘要： A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues.

摘要翻译： 多媒体卡（MMC）单片闪存器件（SCFD）包含一个MMC闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。 微控制器中的中央处理单元（CPU）从小型RAM读取指令，执行初始启动加载程序，从Flash读取更多的页面。 这些页面被小RAM缓冲并写入较大的DRAM。 一旦将扩展引导顺序写入DRAM，CPU将切换一个RAM_BASE位，以使DRAM从DRAM获取指令。 然后从DRAM执行扩展启动顺序，将OS映像从闪存复制到DRAM。 引导代码和控制代码在代码更新操作期间被有选择地覆盖以消除存货问题。

公开(公告)号：US20120202300A1

公开(公告)日：2012-08-09

申请号：US13020339

申请日：2011-02-03

申请人： Frank Yu ,  Eric Hsieh ,  Twu Ares ,  Wei-Lung Hsu

发明人： Frank Yu ,  Eric Hsieh ,  Twu Ares ,  Wei-Lung Hsu

IPC分类号： H01L21/66 ,  B23K31/12

CPC分类号： H01L22/12 ,  H01L24/743 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83855 ,  H01L2224/83908 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/15787 ,  H01L2924/00

摘要： A method for assembling integrated circuit (IC) devices includes dispensing a die attach adhesive onto a surface of a workpiece using a die bonding system, and placing an IC die on the die attach adhesive at surface of the workpiece to form an IC device. A pre-cure bond line thickness (pre-cure BLT) value is automatically optically measured for the die attach adhesive. The IC device is unloaded from the die bonding system after automatically optically measuring. The method can include comparing the pre-cure BLT value to a pre-cure BLT specification range, and if the pre-cure BLT value is outside the pre-cure BLT specification range, adjusting at least one die attach adhesive dispensing parameter based on the pre-cure BLT value for subsequent assembling. The adjusting can be automatic adjusting and the adjustment can be to the Z height parameter of the bond arm.

摘要翻译： 集成电路（IC）装置的组装方法包括使用管芯接合系统将管芯附着粘合剂分散到工件的表面上，并将IC管芯粘附在工件的表面上，形成IC器件。 对于芯片附着粘合剂，自动光学测量预固化粘合线厚度（预固化BLT）值。 自动光学测量后，IC芯片从裸片粘接系统卸载。 该方法可以包括将预固化BLT值与预固化BLT规格范围进行比较，如果预固化BLT值在预固化BLT规格范围之外，则调整至少一个管芯附着粘合剂分配参数，基于 预固化BLT值用于后续组装。 调整可以进行自动调整，调整可以达到接合臂的Z高度参数。

公开(公告)号：US08166221B2

公开(公告)日：2012-04-24

申请号：US12831160

申请日：2010-07-06

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma ,  Jim Chin-Nan Ni ,  Shimon Chen

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma ,  Jim Chin-Nan Ni ,  Shimon Chen

IPC分类号： G06F13/12 ,  G06F13/00

CPC分类号： G06F13/385 ,  G11C16/102 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

摘要： A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices.

摘要翻译： 低功耗闪存设备使用修改后的通用串行总线（USB）3.0协议来降低功耗。 当应用程序中的USB电缆长度短时，位时钟减慢了功率，并且需要预加重。 通过消除8/10位编码器并将同步和成帧字节编码为9位符号来提高数据效率。 数据字节只有在数据中出现一系列6个数据字节时才能通过位填充进行扩展。 标头和有效载荷数据以每个数据字节近8位的形式传输，而成帧是每个符号9位，远远小于每个字节的标准10位。 使用低功率链路层，物理层和缩小协议层。 读卡器转换器集线器允许USB主机访问低功耗USB设备。 只有一个闪存设备被访问，与标准的USB广播相比，将功耗降低到多个设备。

公开(公告)号：US07934074B2

公开(公告)日：2011-04-26

申请号：US11871011

申请日：2007-10-11

申请人： Charles C. Lee ,  Frank Yu ,  Ming-Shiang Shen ,  Abraham C. Ma ,  David Q. Chow

发明人： Charles C. Lee ,  Frank Yu ,  Ming-Shiang Shen ,  Abraham C. Ma ,  David Q. Chow

IPC分类号： G06F12/06

CPC分类号： G06F12/0246 ,  G06F12/0607 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C11/5621 ,  G11C16/0408

摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.

摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。 闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。

公开(公告)号：US07865630B2

公开(公告)日：2011-01-04

申请号：US12426378

申请日：2009-04-20

申请人： I-Kang Frank Yu ,  Abraham C. Ma ,  Charles C. Lee

发明人： I-Kang Frank Yu ,  Abraham C. Ma ,  Charles C. Lee

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/12 ,  G06F9/00

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 多媒体卡/安全数字（MMC / SD）单芯片闪存设备包含一个MMC / SD闪存微控制器和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机MMC / SD总线的MMC / SD事务由MMC / SD闪存微控制器上的总线收发器读取。 响应于MMC / SD事务中的命令，激活在MMC / SD闪存单片机中的CPU上执行的各种例程。 MMC / SD闪存单片机中的闪存控制器将数据从总线收发器传输到闪存大容量存储块以进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US20100283142A1

公开(公告)日：2010-11-11

申请号：US12463729

申请日：2009-05-11

申请人： Chien-Te FENG ,  Frank Yu

发明人： Chien-Te FENG ,  Frank Yu

IPC分类号： H01L23/34 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L21/4878 ,  H01L23/3142 ,  H01L23/4334 ,  H01L23/562 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A mold lock and a method of forming the mold lock are provided. The mold lock is used in an encapsulated semiconductor device and includes a neck and a shaped head integral with the neck. The mold lock can be formed to project above a support component, such as a heat spreader, of the semiconductor device and the neck is formed from the support component. The shaped head is of a greater dimension than the neck and can present a “T” shape in side view or a “Y” shape in side view. A base portion of the neck is seated within the support component. A method is provided for forming the described mold lock.

摘要翻译： 提供了模具锁和形成模具锁的方法。 模具锁用于封装的半导体器件中，并且包括与颈部成一体的颈部和形状的头部。 模具锁可以形成为突出在半导体器件的支撑部件（例如散热器）上方，并且颈部由支撑部件形成。 成形头部的尺寸比颈部大，并且可以在侧视图中呈现“T”形或侧视图中呈“Y”形。 颈部的基部位于支撑部件内。 提供了一种用于形成所述模具锁的方法。

公开(公告)号：US07707321B2

公开(公告)日：2010-04-27

申请号：US11928124

申请日：2007-10-30

申请人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F3/00 ,  G06F13/38

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.

摘要翻译： 扩展的通用串行总线（EUSB）主机通过使用射频（RF）收发器或直接布线轨迹而不是一对传统的USB电缆减少了负载。 减少负荷打开眼睛图案。 EUSB设备使用链接的直接内存访问（DMA）传输内部数据。 DMA控制器中的寄存器指向具有向量条目的向量表，每个向量表指向一个目的地和一个源。 源是内存组的内存表。 内存表有几个内存段的条目。 每个存储表条目具有指向存储器段的指针和段的字节计数。 一旦片段中的所有字节都被传送，该条目中的标志表示在存储器组中跟随其他内存段的时间。 读取END标志时，向量表前进到下一个向量条目，并处理另一个内存段的内存组。