发明授权
- 专利标题: Semiconductor structure for low parasitic gate capacitance
- 专利标题(中): 用于低寄生栅极电容的半导体结构
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申请号: US11738666申请日: 2007-04-23
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公开(公告)号: US07709910B2公开(公告)日: 2010-05-04
- 发明人: William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
- 申请人: William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Scully, Scott, Murphy & Presser, P.C.
- 代理商 H. Daniel Schnurmann
- 主分类号: H01L29/78
- IPC分类号: H01L29/78
摘要:
A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.
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