公开(公告)号：US08438509B2

公开(公告)日：2013-05-07

申请号：US12621564

申请日：2009-11-19

申请人： William K. Hensen ,  Michael D. Hulvey ,  Amit Kumar ,  Jeanne-Tania Sucharitaves ,  Amanda L. Tessier

发明人： William K. Hensen ,  Michael D. Hulvey ,  Amit Kumar ,  Jeanne-Tania Sucharitaves ,  Amanda L. Tessier

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  H01L27/0207 ,  Y02P90/265

摘要： A method of automated generation of oxide pillar (PX) slot shapes of a PX layer within silicon-on-insulator (SOI) structures that includes generating a placement grid on recess oxide (RX) shapes, creating PX placement markers on the placement grid along a perimeter of the RX shapes, filtering the PX placement markers, generating a PX slot shape corresponding to each filtered PX placement marker on the RX shapes, correcting location errors associated with the generated PX slot shapes, generating PX slot shapes on RX shapes of a predetermined size for which PX slot shapes were not generated, performing a verification operation of the PX slot shapes, and outputting the PX layer including the verified PX slot shapes.

摘要翻译： 在绝缘体上硅（SOI）结构中自动生成PX层的氧化物柱（PX）槽形状的方法，其包括在凹陷氧化物（RX）形状上产生放置栅格，在放置栅格上产生PX放置标记 RX形状的周边，对PX位置标记进行滤波，产生与RX形状上的每个滤波PX放置标记相对应的PX槽形状，校正与所产生的PX槽形状相关联的位置误差，在RX形状上产生PX槽形状 不产生PX槽形状的预定尺寸，执行PX槽形状的验证操作，并输出包括验证的PX槽形状的PX层。

公开(公告)号：US07888738B2

公开(公告)日：2011-02-15

申请号：US12685690

申请日：2010-01-12

申请人： Amanda L. Tessier ,  Brian L. Tessier ,  Bryant C. Colwill

发明人： Amanda L. Tessier ,  Brian L. Tessier ,  Bryant C. Colwill

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/743 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide a microelectronic structure including a conductive element contacting a bulk semiconductor region of a substrate, the bulk semiconductor region being separated from a semiconductor-on-insulator (“SOI”) layer of the substrate by a buried dielectric layer. The microelectronic structure includes a trench isolation region overlying the buried dielectric layer, the trench isolation region sharing an edge with the SOI layer; a conformal layer overlying the trench isolation region, the conformal layer having a top surface and an opening defining a wall extending from the top surface towards the trench isolation region, the top surface including a lip portion adjacent to the wall; a dielectric layer overlying the top surface of the conformal layer; and a conductive element in conductive communication with the bulk semiconductor region, the conductive element consisting essentially of at least one of a semiconductor, a metal, and a conductive compound of a metal, and extending through the dielectric layer, the opening in the conformal layer, the trench isolation region, and the buried dielectric layer, and the conductive element contacting the lip portion.

摘要翻译： 本发明的实施例提供一种微电子结构，其包括接触衬底的体半导体区域的导电元件，所述体半导体区域通过掩埋介电层与衬底的绝缘体上半导体（“SOI”）层分离。 微电子结构包括覆盖掩埋介质层的沟槽隔离区域，沟槽隔离区域与SOI层共享边缘; 覆盖所述沟槽隔离区域的共形层，所述共形层具有顶表面和限定从所述顶表面朝向所述沟槽隔离区域延伸的壁的开口，所述顶表面包括邻近所述壁的唇部; 覆盖保形层的顶表面的电介质层; 以及与体半导体区域导电连通的导电元件，所述导电元件基本上由金属的半导体，金属和导电化合物中的至少一种组成并且延伸穿过所述电介质层，所述共形层中的所述开口 沟槽隔离区和埋入介质层，导电元件与唇部接触。

公开(公告)号：US20090311855A1

公开(公告)日：2009-12-17

申请号：US12544425

申请日：2009-08-20

申请人： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

发明人： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

IPC分类号： H01L21/28

CPC分类号： H01L21/823807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823864 ,  H01L29/7843

摘要： A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.

摘要翻译： 提供了在金属氧化物半导体场效应晶体管（MOSFET）中制造栅极结构的方法及其结构。 MOSFET可以是n掺杂或p掺杂的。 设置在基板上的栅极结构包括多个栅极。 多个栅极中的每一个与相邻栅极分开一垂直空间。 该方法将填充每个垂直空间的至少一个双层衬垫沉积在栅极结构上。 双层衬垫包括至少两个薄的高密度等离子体（HDP）膜。 两种HDP膜的沉积在单个HDP化学气相沉积（CVD）工艺中发生。 双层衬垫具有有利于与等离子体增强化学气相沉积（PECVD）膜耦合以在栅极结构中形成三层或二次层膜堆叠的性质。

公开(公告)号：US20090101980A1

公开(公告)日：2009-04-23

申请号：US11875222

申请日：2007-10-19

申请人： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

发明人： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

IPC分类号： H01L27/088 ,  H01L21/3205

CPC分类号： H01L21/823807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823864 ,  H01L29/7843

摘要： A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.

摘要翻译： 提供了在金属氧化物半导体场效应晶体管（MOSFET）中制造栅极结构的方法及其结构。 MOSFET可以是n掺杂或p掺杂的。 设置在基板上的栅极结构包括多个栅极。 多个栅极中的每一个与相邻栅极分开一垂直空间。 该方法将填充每个垂直空间的至少一个双层衬垫沉积在栅极结构上。 双层衬垫包括至少两个薄的高密度等离子体（HDP）膜。 两种HDP膜的沉积在单个HDP化学气相沉积（CVD）工艺中发生。 双层衬垫具有有利于与等离子体增强化学气相沉积（PECVD）膜耦合以在栅极结构中形成三层或二次层膜堆叠的性质。

公开(公告)号：US20080258234A1

公开(公告)日：2008-10-23

申请号：US11738666

申请日：2007-04-23

申请人： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

发明人： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

IPC分类号： H01L21/285 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

摘要： A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.

摘要翻译： 半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。 氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平 。 由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。 栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。

公开(公告)号：US07718514B2

公开(公告)日：2010-05-18

申请号：US11769912

申请日：2007-06-28

申请人： Amanda L. Tessier ,  Bryant C. Colwill ,  Brian L. Tessier

发明人： Amanda L. Tessier ,  Bryant C. Colwill ,  Brian L. Tessier

IPC分类号： H01L21/20

CPC分类号： H01L21/84 ,  H01L21/743 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided of forming a conductive via in contact with a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region. The trench isolation region may share an edge with an SOI layer of the substrate. Desirably, a dielectric layer is deposited over a top surface of the conformal layer and the trench isolation region. A second opening can then be formed which extends through the dielectric layer and the first opening in the conformal layer. Desirably, portions of the bulk semiconductor region and the top surface of the conformal layer are exposed within the second opening. The second opening can then be filled with at least one of a metal or a semiconductor to form a conductive element contacting the exposed portions of the bulk semiconductor region and the top surface of the conformal layer.

摘要翻译： 提供了一种形成与绝缘体上半导体（“SOI”）衬底的体半导体区域接触的导电通孔的方法。 在覆盖沟槽隔离区域的保形层中形成第一开口。 沟槽隔离区可以与衬底的SOI层共享边缘。 期望地，在保形层和沟槽隔离区的顶表面上沉积电介质层。 然后可以形成延伸穿过电介质层和保形层中的第一开口的第二开口。 理想的是，半导体区域的部分和保形层的顶表面在第二开口内露出。 然后可以用金属或半导体中的至少一个填充第二开口，以形成接触体半导体区域的暴露部分和保形层顶表面的导电元件。

公开(公告)号：US20100109119A1

公开(公告)日：2010-05-06

申请号：US12685690

申请日：2010-01-12

申请人： Amanda L. Tessier ,  Bryant C. Colwill ,  Brian L. Tessier

发明人： Amanda L. Tessier ,  Bryant C. Colwill ,  Brian L. Tessier

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/743 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide a microelectronic structure including a conductive element contacting a bulk semiconductor region of a substrate, the bulk semiconductor region being separated from a semiconductor-on-insulator (“SOI”) layer of the substrate by a buried dielectric layer. The microelectronic structure includes a trench isolation region overlying the buried dielectric layer, the trench isolation region sharing an edge with the SOI layer; a conformal layer overlying the trench isolation region, the conformal layer having a top surface and an opening defining a wall extending from the top surface towards the trench isolation region, the top surface including a lip portion adjacent to the wall; a dielectric layer overlying the top surface of the conformal layer; and a conductive element in conductive communication with the bulk semiconductor region, the conductive element consisting essentially of at least one of a semiconductor, a metal, and a conductive compound of a metal, and extending through the dielectric layer, the opening in the conformal layer, the trench isolation region, and the buried dielectric layer, and the conductive element contacting the lip portion.

摘要翻译： 本发明的实施例提供一种微电子结构，其包括接触衬底的体半导体区域的导电元件，所述体半导体区域通过掩埋介电层与衬底的绝缘体上半导体（“SOI”）层分离。 微电子结构包括覆盖掩埋介质层的沟槽隔离区域，沟槽隔离区域与SOI层共享边缘; 覆盖所述沟槽隔离区域的共形层，所述共形层具有顶表面和限定从所述顶表面朝向所述沟槽隔离区域延伸的壁的开口，所述顶表面包括邻近所述壁的唇部; 覆盖保形层的顶表面的电介质层; 以及与体半导体区域导电连通的导电元件，所述导电元件基本上由金属的半导体，金属和导电化合物中的至少一种组成并且延伸穿过所述电介质层，所述共形层中的所述开口 沟槽隔离区和埋入介质层，导电元件与唇部接触。

公开(公告)号：US07709910B2

公开(公告)日：2010-05-04

申请号：US11738666

申请日：2007-04-23

申请人： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

发明人： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

IPC分类号： H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

摘要： A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.

摘要翻译： 半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。 氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平 。 由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。 栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。

公开(公告)号：US20090256207A1

公开(公告)日：2009-10-15

申请号：US12102333

申请日：2008-04-14

申请人： Xiaomeng Chen ,  Bachir Dirahoui ,  William K. Henson ,  Michael D. Hulvey ,  Amit Kumar ,  Mahender Kumar ,  Amanda L. Tessier ,  Clement H. Wann

发明人： Xiaomeng Chen ,  Bachir Dirahoui ,  William K. Henson ,  Michael D. Hulvey ,  Amit Kumar ,  Mahender Kumar ,  Amanda L. Tessier ,  Clement H. Wann

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795

摘要： Disclosed herein is a transistor comprising a first fin having a first gate electrode disposed across the first fin; the gate electrode contacting opposing surfaces of the fin; and a planar oxide layer having a second gate electrode disposed across the planar oxide layer to form a planar metal oxide semiconductor field effect transistor; the first fin and the planar oxide layer being disposed upon a surface of a wafer.

摘要翻译： 本文公开了一种晶体管，包括：第一鳍片，其具有横跨第一鳍片设置的第一栅电极; 所述栅电极接触所述翅片的相对表面; 以及平面氧化物层，具有跨过所述平面氧化物层设置的第二栅极，以形成平面金属氧化物半导体场效应晶体管; 第一鳍片和平面氧化物层设置在晶片的表面上。

公开(公告)号：US20100269085A1

公开(公告)日：2010-10-21

申请号：US12621564

申请日：2009-11-19

申请人： William Kirklen Henson ,  Michael D. Hulvey ,  Amit Kumar ,  Jeanne-Tania Sucharitaves ,  Amanda L. Tessier

发明人： William Kirklen Henson ,  Michael D. Hulvey ,  Amit Kumar ,  Jeanne-Tania Sucharitaves ,  Amanda L. Tessier

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  H01L27/0207 ,  Y02P90/265

摘要： A method of automated generation of oxide pillar (PX) slot shapes of a PX layer within silicon-on-insulator (SOI) structures that includes generating a placement grid on recess oxide (RX) shapes, creating PX placement markers on the placement grid along a perimeter of the RX shapes, filtering the PX placement markers, generating a PX slot shape corresponding to each filtered PX placement marker on the RX shapes, correcting location errors associated with the generated PX slot shapes, generating PX slot shapes on RX shapes of a predetermined size for which PX slot shapes were not generated, performing a verification operation of the PX slot shapes, and outputting the PX layer including the verified PX slot shapes.

摘要翻译： 在绝缘体上硅（SOI）结构中自动生成PX层的氧化物柱（PX）槽形状的方法，其包括在凹陷氧化物（RX）形状上产生放置栅格，在放置栅格上产生PX放置标记 RX形状的周边，对PX位置标记进行滤波，产生与RX形状上的每个滤波PX放置标记相对应的PX槽形状，校正与所产生的PX槽形状相关联的位置误差，在RX形状上产生PX槽形状 不产生PX槽形状的预定尺寸，执行PX槽形状的验证操作，并输出包括验证的PX槽形状的PX层。