发明授权
US07716623B1 Programmable logic device architectures and methods for implementing logic in those architectures
有权
可编程逻辑器件架构和方法，用于在这些架构中实现逻辑
- 专利标题： Programmable logic device architectures and methods for implementing logic in those architectures
- 专利标题（中）： 可编程逻辑器件架构和方法，用于在这些架构中实现逻辑
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申请号： US12580038申请日： 2009-10-15
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公开(公告)号： US07716623B1公开(公告)日： 2010-05-11
- 发明人: Tim Vanderhoek , Vaughn Betz , David Cashman , David Lewis , Michael Hutton
- 申请人： Tim Vanderhoek , Vaughn Betz , David Cashman , David Lewis , Michael Hutton
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Ropes & Gray LLP
- 代理商 Robert R. Jackson
- 主分类号： H03K17/693
- IPC分类号： H03K17/693
摘要：
A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.
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