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    Programmable logic device architectures and methods for implementing logic in those architectures
    1.
    发明授权
    Programmable logic device architectures and methods for implementing logic in those architectures 有权
    可编程逻辑器件架构和方法，用于在这些架构中实现逻辑

    公开(公告)号：US07716623B1

    公开(公告)日：2010-05-11

    申请号：US12580038

    申请日：2009-10-15

    申请人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    发明人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    IPC分类号： H03K17/693

    CPC分类号： H03K19/17736

    摘要： A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

    摘要翻译： 可编程逻辑器件（“PLD”）架构包括被称为逻辑阵列块（LAB）“的群集在一起的逻辑元件（”LE“）。 为了节省面积，与现有技术相比，减少或消除了局部反馈资源（用于将LAB中的LE的输出反馈到LAB中的LE的输入）。 因为在LAB中一起工作的LE的任何LE输出到LE输入连接的所有（或至少更多）必须通过LAB的通用输入路由资源路由，所以保存那些 资源。 例如，通过在确定在LAB中一起实现哪些逻辑功能时，更重要的是找到具有共同输入的逻辑功能。

    Programmable logic device architectures and methods for implementing logic in those architectures
    2.
    发明授权
    Programmable logic device architectures and methods for implementing logic in those architectures 有权
    可编程逻辑器件架构和方法，用于在这些架构中实现逻辑

    公开(公告)号：US07619443B1

    公开(公告)日：2009-11-17

    申请号：US11356762

    申请日：2006-02-16

    申请人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    发明人： Tim Vanderhoek ,  Vaughn Betz ,  David Cashman ,  David Lewis ,  Michael Hutton

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

    摘要翻译： 可编程逻辑器件（“PLD”）架构包括被称为逻辑阵列块（LABs“）的集群在一起的逻辑元件（”LE“）。为了保存区域，本地反馈资源（用于将LAB中的LE的输出馈送回到 与现有技术相比，减少或消除了LAB中的LE的输入），因为在LAB中一起工作的LE的任何LE输出到LE输入连接的所有（或至少更多）必须是 通过LAB的通用输入路由资源路由，重要的是保存这些资源，例如，通过更加重视找到具有共同输入的逻辑功能，在决定在 劳顾会

    Distributed memory in field-programmable gate array integrated circuit devices
    7.
    发明授权
    Distributed memory in field-programmable gate array integrated circuit devices 有权
    现场可编程门阵列集成电路器件中的分布式存储器

    公开(公告)号：US07656191B2

    公开(公告)日：2010-02-02

    申请号：US12156403

    申请日：2008-05-30

    申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    IPC分类号： H03K19/177

    CPC分类号： G11C7/1045 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

    摘要翻译： 用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。 例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。 作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。 显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

    Distributed memory in field-programmable gate array integrated circuit devices
    8.
    发明申请
    Distributed memory in field-programmable gate array integrated circuit devices 有权
    现场可编程门阵列集成电路器件中的分布式存储器

    公开(公告)号：US20080231316A1

    公开(公告)日：2008-09-25

    申请号：US12156403

    申请日：2008-05-30

    申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    IPC分类号： H03K19/177

    CPC分类号： G11C7/1045 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

    摘要翻译： 用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。 例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。 作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。 显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。