发明授权
US07718482B2 CD gate bias reduction and differential N+ poly doping for CMOS circuits
有权
用于CMOS电路的CD栅偏压减小和差分N +多掺杂
- 专利标题： CD gate bias reduction and differential N+ poly doping for CMOS circuits
- 专利标题（中）： 用于CMOS电路的CD栅偏压减小和差分N +多掺杂
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申请号： US11928872申请日： 2007-10-30
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公开(公告)号： US07718482B2公开(公告)日： 2010-05-18
- 发明人: Shashank Ekbote , Borna Obradovic , Greg C. Baldwin
- 申请人： Shashank Ekbote , Borna Obradovic , Greg C. Baldwin
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238
摘要：
A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.
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