公开(公告)号：US08114729B2

公开(公告)日：2012-02-14

申请号：US11870255

申请日：2007-10-10

申请人： Shashank Ekbote ,  Kamel Benaissa ,  Greg C. Baldwin ,  Borna Obradovic

发明人： Shashank Ekbote ,  Kamel Benaissa ,  Greg C. Baldwin ,  Borna Obradovic

IPC分类号： H01L21/8238

CPC分类号： G11C11/412 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/32155 ,  H01L21/823842 ,  H01L27/0922 ,  Y10S257/903

摘要： A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant.

摘要翻译： 一种制造CMOS集成电路的方法及其集成电路包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，以及在栅极电介质上形成多晶硅。 多晶硅层的一部分被掩蔽，并且执行第一掺杂剂类型的预栅极蚀刻注入到多晶硅层的未屏蔽部分中，其中多晶硅层的掩模部分被保护免受第一掺杂剂的影响。 多晶硅层被图案化以形成多个多晶硅栅极和多条多晶硅线，其中掩模部分包括将PMOS器件的多晶硅栅极耦合到NMOS器件的多晶硅栅极的至少一条多晶硅线路。 然后完成集成电路的制造，其中集成电路包括形成在掩模部分中的至少一个第一区域，该第一区域在预栅极蚀刻植入物的多晶硅栅极中缺少第一掺杂剂，以及形成在未掩模部分中的至少一个第二区域 在栅极蚀刻植入物的多晶硅栅极中具有第一掺杂剂。

公开(公告)号：US07718482B2

公开(公告)日：2010-05-18

申请号：US11928872

申请日：2007-10-30

申请人： Shashank Ekbote ,  Borna Obradovic ,  Greg C. Baldwin

发明人： Shashank Ekbote ,  Borna Obradovic ,  Greg C. Baldwin

IPC分类号： H01L21/8238

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823842 ,  H01L27/11

摘要： A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.

摘要翻译： 一种制造CMOS集成电路的方法包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，在栅极介质层上形成多晶硅层。 图案化多晶硅层，同时未掺杂以形成包含栅极的多个多晶硅。 第一模式用于保护多个PMOS器件，并且执行第一n型注入以掺杂多个NMOS器件的栅极和源极/漏极区域。 第二模式用于保护PMOS器件以及用于多个NMOS器件的一部分的源极/漏极和栅极，并且执行第二n型注入以掺杂其它NMOS器件的栅极。

公开(公告)号：US20090096031A1

公开(公告)日：2009-04-16

申请号：US11870255

申请日：2007-10-10

申请人： Shashank EKBOTE ,  Kamel Benaissa ,  Greg C. Baldwin ,  Borna Obradovic

发明人： Shashank EKBOTE ,  Kamel Benaissa ,  Greg C. Baldwin ,  Borna Obradovic

IPC分类号： H01L27/11 ,  H01L21/3205

CPC分类号： G11C11/412 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/32155 ,  H01L21/823842 ,  H01L27/0922 ,  Y10S257/903

摘要： A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant.

摘要翻译： 一种制造CMOS集成电路的方法及其集成电路包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，以及在栅极电介质上形成多晶硅。 多晶硅层的一部分被掩蔽，并且执行第一掺杂剂类型的预栅极蚀刻注入到多晶硅层的未屏蔽部分中，其中多晶硅层的掩模部分被保护免受第一掺杂剂的影响。 多晶硅层被图案化以形成多个多晶硅栅极和多条多晶硅线，其中掩模部分包括将PMOS器件的多晶硅栅极耦合到NMOS器件的多晶硅栅极的至少一条多晶硅线路。 然后完成集成电路的制造，其中集成电路包括形成在掩模部分中的至少一个第一区域，该第一区域在预栅极蚀刻植入物的多晶硅栅极中缺少第一掺杂剂，以及形成在未掩模部分中的至少一个第二区域 在栅极蚀刻植入物的多晶硅栅极中具有第一掺杂剂。

公开(公告)号：US20090098694A1

公开(公告)日：2009-04-16

申请号：US11928872

申请日：2007-10-30

申请人： Shashank Ekbote ,  Borna Obradovic ,  Greg C. Baldwin

发明人： Shashank Ekbote ,  Borna Obradovic ,  Greg C. Baldwin

IPC分类号： H01L21/8238 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823842 ,  H01L27/11

摘要： A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.

摘要翻译： 一种制造CMOS集成电路的方法包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，在栅极介质层上形成多晶硅层。 图案化多晶硅层，同时未掺杂以形成包含栅极的多个多晶硅。 第一模式用于保护多个PMOS器件，并且执行第一n型注入以掺杂多个NMOS器件的栅极和源极/漏极区域。 第二模式用于保护PMOS器件以及用于多个NMOS器件的一部分的源极/漏极和栅极，并且执行第二n型注入以掺杂其它NMOS器件的栅极。

公开(公告)号：US06333238B2

公开(公告)日：2001-12-25

申请号：US09729686

申请日：2000-12-06

申请人： Greg C. Baldwin ,  Alwin J. Tsao

发明人： Greg C. Baldwin ,  Alwin J. Tsao

IPC分类号： H01L2702

CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C7/06 ,  H01L27/0802

摘要： An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2), a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.

摘要翻译： 包含电阻和电阻本身的集成电路。 电路包括衬底（2），衬底上的半导体电阻（3）和设置在衬底上的电绝缘材料层（5），半导体电阻器具有延伸穿过其中的至少一个触点（11,13,15） 到半导体电阻器，该触头具有一个电路，其中延伸到半导体电阻的端部并与其形成界面。 半导体电阻器具有半导体电阻体，优选掺杂多晶硅，具有正或负温度系数电阻中的一个和电阻头。 电阻头基本上由金属互连的电气路径，触点，然后与电阻体接触并与电阻体接触，电阻头具有正或负温度系数的电阻。

公开(公告)号：US07888227B2

公开(公告)日：2011-02-15

申请号：US12137649

申请日：2008-06-12

申请人： Robert L. Pitts ,  Greg C. Baldwin

发明人： Robert L. Pitts ,  Greg C. Baldwin

IPC分类号： H01L21/20

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

摘要翻译： 集成电路电感器（5）通过将具有连续通孔（200）的集成电路中的各种金属层（10）互连而形成。 使用连续通孔（200）改善了与现有高频应用方法相比的Q因子。 连续通孔的连续长度应大于电感器（5）长度的三分之一。

公开(公告)号：US20080286933A1

公开(公告)日：2008-11-20

申请号：US12137649

申请日：2008-06-12

申请人： Robert L. Pitts ,  Greg C. Baldwin

发明人： Robert L. Pitts ,  Greg C. Baldwin

IPC分类号： H01L21/02

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

摘要翻译： 集成电路电感器（5）通过将具有连续通孔（200）的集成电路中的各种金属层（10）互连而形成。 使用连续通孔（200）改善了与现有高频应用方法相比的Q因子。 连续通孔的连续长度应大于电感器（5）长度的三分之一。

公开(公告)号：US07994009B2

公开(公告)日：2011-08-09

申请号：US12492743

申请日：2009-06-26

申请人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

发明人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

IPC分类号： H01L21/8234

CPC分类号： H01L21/823437 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659

摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

摘要翻译： 公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电特性的晶体管。 还公开了同时制造这两种晶体管的工艺。 公开了同时形成对称和不对称晶体管的工艺的具体实施例。

公开(公告)号：US20110133880A1

公开(公告)日：2011-06-09

申请号：US13027903

申请日：2011-02-15

申请人： Robert L. Pitts ,  Greg C. Baldwin

发明人： Robert L. Pitts ,  Greg C. Baldwin

IPC分类号： H01F5/00

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

摘要翻译： 集成电路电感器（5）通过将具有连续通孔（200）的集成电路中的各种金属层（10）互连而形成。 使用连续通孔（200）改善了与现有高频应用方法相比的Q因子。 连续通孔的连续长度应大于电感器（5）长度的三分之一。

公开(公告)号：US07400025B2

公开(公告)日：2008-07-15

申请号：US10843952

申请日：2004-05-11

申请人： Robert L. Pitts ,  Greg C. Baldwin

发明人： Robert L. Pitts ,  Greg C. Baldwin

IPC分类号： H01L27/108

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

摘要翻译： 集成电路电感器（5）通过将具有连续通孔（200）的集成电路中的各种金属层（10）互连而形成。 使用连续通孔（200）改善了与现有高频应用方法相比的Q因子。 连续通孔的连续长度应大于电感器（5）长度的三分之一。