发明授权
US07730445B2 Pattern data verification method for semiconductor device, computer-readable recording medium having pattern data verification program for semiconductor device recorded, and semiconductor device manufacturing method
失效
用于半导体器件的图案数据验证方法，具有用于半导体器件的图案数据验证程序的计算机可读记录介质和半导体器件制造方法
- 专利标题： Pattern data verification method for semiconductor device, computer-readable recording medium having pattern data verification program for semiconductor device recorded, and semiconductor device manufacturing method
- 专利标题（中）： 用于半导体器件的图案数据验证方法，具有用于半导体器件的图案数据验证程序的计算机可读记录介质和半导体器件制造方法
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申请号： US11798725申请日： 2007-05-16
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公开(公告)号： US07730445B2公开(公告)日： 2010-06-01
- 发明人: Shigeki Nojima
- 申请人： Shigeki Nojima
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权： JP2006-137980 20060517
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A pattern data verification method for a semiconductor device, including extracting, from design data, design data corresponding to an edge portion of a mask pattern to obtain an edge portion of a pattern on a substrate to be processed, when the pattern is obtained on the substrate to be processed by using at least two masks each having the mask pattern corresponding to the design data, setting allowable errors with respect to the extracted design data and the design data which is not extracted, respectively, calculating a pattern formed on the substrate to be processed by using at least one mask by process simulation, and comparing an error between the pattern calculated by the simulation and the design data with the allowable error set for the design data.
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