发明授权
US07737983B2 GPU pipeline multiple level synchronization controller processor and method
有权
GPU管道多级同步控制器处理器和方法
- 专利标题: GPU pipeline multiple level synchronization controller processor and method
- 专利标题(中): GPU管道多级同步控制器处理器和方法
-
申请号: US11552693申请日: 2006-10-25
-
公开(公告)号: US07737983B2公开(公告)日: 2010-06-15
- 发明人: John Brothers , Timour Paltashev , Hsilin Huang , Boris Prokopenko , Qunfeng (Fred) Liao
- 申请人: John Brothers , Timour Paltashev , Hsilin Huang , Boris Prokopenko , Qunfeng (Fred) Liao
- 申请人地址: TW Hsin-Tien, Taipei
- 专利权人: Via Technologies, Inc.
- 当前专利权人: Via Technologies, Inc.
- 当前专利权人地址: TW Hsin-Tien, Taipei
- 代理机构: Thomas, Kayden, Horstemeyer & Risley
- 主分类号: G06F1/20
- IPC分类号: G06F1/20 ; G06T1/00
摘要:
A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.
公开/授权文献
信息查询