发明授权
- 专利标题: Method for reducing silicide defects in integrated circuits
- 专利标题(中): 降低集成电路中硅化物缺陷的方法
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申请号: US12124177申请日: 2008-05-21
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公开(公告)号: US07745320B2公开(公告)日: 2010-06-29
- 发明人: Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
- 申请人: Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
- 申请人地址: SG Singapore
- 专利权人: Chartered Semiconductor Manufacturing, Ltd.
- 当前专利权人: Chartered Semiconductor Manufacturing, Ltd.
- 当前专利权人地址: SG Singapore
- 代理机构: Horizon IP Pte Ltd
- 主分类号: H01L29/00
- IPC分类号: H01L29/00 ; H01L21/311
摘要:
A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
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