发明授权
- 专利标题： FIFO memory error circuit and method
- 专利标题（中）： FIFO存储器错误电路和方法
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申请号： US10891339申请日： 2004-07-14
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公开(公告)号： US07752506B1公开(公告)日： 2010-07-06
- 发明人: Rishi Yadav
- 申请人： Rishi Yadav
- 申请人地址： US CA San Jose
- 专利权人： Cypress Semiconductor Corporation
- 当前专利权人： Cypress Semiconductor Corporation
- 当前专利权人地址： US CA San Jose
- 主分类号： G06F11/00
- IPC分类号： G06F11/00
摘要：
A FIFO memory error circuit has a read pointer coupled to a FIFO memory. The read pointer has a logic high output once every FIFO memory cycle. A write pointer is coupled to the FIFO memory and has a logic high output once every FIFO memory cycle. An error detector has a first input coupled to the read pointer and a second input coupled to the write pointer.
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