公开(公告)号：US07752506B1

公开(公告)日：2010-07-06

申请号：US10891339

申请日：2004-07-14

申请人： Rishi Yadav

发明人： Rishi Yadav

IPC分类号： G06F11/00

CPC分类号： G06F11/0751 ,  G06F11/073

摘要： A FIFO memory error circuit has a read pointer coupled to a FIFO memory. The read pointer has a logic high output once every FIFO memory cycle. A write pointer is coupled to the FIFO memory and has a logic high output once every FIFO memory cycle. An error detector has a first input coupled to the read pointer and a second input coupled to the write pointer.

摘要翻译： FIFO存储器错误电路具有耦合到FIFO存储器的读指针。 每个FIFO存储器周期，读指针都具有逻辑高输出。 写入指针耦合到FIFO存储器，并且每FIFO存储周期都具有逻辑高输出。 误差检测器具有耦合到读指针的第一输入和耦合到写指针的第二输入。

公开(公告)号：US07421559B1

公开(公告)日：2008-09-02

申请号：US11015959

申请日：2004-12-16

申请人： Rishi Yadav

发明人： Rishi Yadav

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G11C7/1075

摘要： A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access arbitration is performed. The synchronous multi-port memory may also include selection logic coupled with the plurality of ports and the memory array to arbitrate among a plurality of contending memory access requests, to select a prevailing memory access request and to implement memory access controls.

摘要翻译： 一种同步多端口存储器，包括与存储器阵列耦合的多个端口，所述多个端口中的每一个端口包括在执行存储器访问仲裁的同时延迟存储器访问的延迟级。 同步多端口存储器还可以包括与多个端口耦合的选择逻辑和存储器阵列以在多个竞争存储器访问请求之间进行仲裁，以选择主要的存储器访问请求并实现存储器访问控制。

公开(公告)号：US08527729B1

公开(公告)日：2013-09-03

申请号：US13340602

申请日：2011-12-29

申请人： Rishi Yadav

发明人： Rishi Yadav

IPC分类号： G06F12/00

CPC分类号： G11C7/1075

摘要： A multi-port memory, comprising: a plurality of ports, each port including port input logic that generates a write enable value from received control signals, and a delay stage coupled to store the write enable value from the input stage, and configured to force the write enable value to a disable state in response to an asserted busy signal of the port; and an arbitration circuit coupled to the ports that arbitrates contending accesses to the ports by de-asserting a busy signal to one port, and asserting a busy signal for all other ports.

摘要翻译： 一种多端口存储器，包括：多个端口，每个端口包括从接收到的控制信号产生写使能值的端口输入逻辑，以及耦合以从输入级存储写使能值的延迟级，并且被配置为强制 响应于所述端口的被断言的忙信号将所述写使能值设置为禁用状态; 以及耦合到端口的仲裁电路，通过将忙信号解除为一个端口来仲裁对端口的竞争访问，并且为所有其他端口断言忙信号。

公开(公告)号：US08060721B1

公开(公告)日：2011-11-15

申请号：US12191102

申请日：2008-08-13

申请人： Rishi Yadav

发明人： Rishi Yadav

IPC分类号： G06F12/00

CPC分类号： G11C7/1075

摘要： A method of and apparatus for arbitrating a memory access conflict to a memory array. The apparatus may include selection logic coupled with a plurality of ports and a memory array to arbitrate among a plurality of contending memory access requests and to conditionally block write data from accessing the memory array when write data arrives late in time.

摘要翻译： 一种用于将存储器访问冲突仲裁到存储器阵列的方法和装置。 该装置可以包括与多个端口耦合的选择逻辑和存储器阵列，用于在多个竞争存储器访问请求之间进行仲裁，并且当写入数据迟到时有条件地阻止写入数据访问存储器阵列。

公开(公告)号：US08555011B1

公开(公告)日：2013-10-08

申请号：US13297171

申请日：2011-11-15

申请人： Rishi Yadav

发明人： Rishi Yadav

IPC分类号： G06F12/00

CPC分类号： G11C7/1075

摘要： A method of and apparatus for arbitrating a memory access conflict to a memory array. The apparatus may include selection logic coupled with a plurality of ports and a memory array to arbitrate among a plurality of contending memory access requests and to conditionally block write data from accessing the memory array when write data arrives late in time.

摘要翻译： 一种用于将存储器访问冲突仲裁到存储器阵列的方法和装置。 该装置可以包括与多个端口耦合的选择逻辑和存储器阵列，用于在多个竞争存储器访问请求之间进行仲裁，并且当写入数据迟到时有条件地阻止写入数据访问存储器阵列。

公开(公告)号：US07962698B1

公开(公告)日：2011-06-14

申请号：US11523503

申请日：2006-09-18

申请人： Rishi Yadav ,  Alan Refalo

发明人： Rishi Yadav ,  Alan Refalo

IPC分类号： G06F12/00

CPC分类号： G06F13/4234

摘要： An embodiment of the present invention is directed to a method of deterministic collision detection involving at least two ports. The method includes receiving a read/write operation at a first data rate at a first port of a multi-port device, receiving a read/write operation at a second data rate at a second port of the multi-port device, detecting a collision between the first port and the second port if a same address space is accessed by the first port and the second port coincidentally, asserting a busy signal at least one of said first port and said second port a number of clock cycles after detecting said collision, storing an address location of said address space in a memory register, and deterministically report the collision using the address location and the number of clock cycles.

摘要翻译： 本发明的实施例涉及涉及至少两个端口的确定性碰撞检测的方法。 该方法包括在多端口设备的第一端口处以第一数据速率接收读/写操作，在多端口设备的第二端口处以第二数据速率接收读/写操作，检测碰撞 在第一端口和第二端口之间，如果第一端口和第二端口同时访问相同的地址空间，则在检测到所述冲突之后将所述第一端口和所述第二端口中的至少一个断言为多个时钟周期， 将所述地址空间的地址位置存储在存储器寄存器中，并且使用地址位置和时钟周期的数量确定性地报告冲突。