A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.