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1.发明授权Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance 失效用于评估存储阵列性能的字线到位线输出定时环形振荡器电路公开(公告)号：US07760565B2
公开(公告)日：2010-07-20
申请号：US11781994
申请日：2007-07-24
申请人： Jente B. Kuang , Jerry C. Kao , Hung C. Ngo , Kevin J. Nowka , Liang-Teck Pang , Jayakumaran Sivagnaname
发明人： Jente B. Kuang , Jerry C. Kao , Hung C. Ngo , Kevin J. Nowka , Liang-Teck Pang , Jayakumaran Sivagnaname
CPC分类号： G11C29/50 , G01R31/31937 , G11C29/50012 , G11C2029/1202 , G11C2029/1204
摘要： A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.
摘要翻译： 用于评估存储单元访问时间的字线到位线定时环形振荡器电路提供关于内部位线访问定时的数据，特别是总字线选择到位线读出输出定时。 存储阵列的列以环形连接，形成环形振荡器。 每列的位线读取电路输出连接到下一列的字线选择输入，环绕环反转，从而形成环形振荡器。 环形振荡器的振荡周期由第一相的总字线选择到位线读取电路输出定时和另一相的预充电间隔时间决定，而位线读取时序主导。 该电路可以应用于小信号存储阵列，其中包括在环形振荡器周期内的读出放大器定时，或者包括读取评估电路时序的大信号存储阵列。
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2.发明申请Wordline-To-Bitline Output Timing Ring Oscillator Circuit for Evaluating Storage Array Performance 失效用于评估存储阵列性能的字线到位线输出定时环形振荡器电路公开(公告)号：US20090027065A1
公开(公告)日：2009-01-29
申请号：US11781994
申请日：2007-07-24
申请人： Jente B. Kuang , Jerry C. Keo , Hung C. Ngo , Kevin J. Nowka , Liang-Teck Pang , Jayakumaran Sivagnaname
发明人： Jente B. Kuang , Jerry C. Keo , Hung C. Ngo , Kevin J. Nowka , Liang-Teck Pang , Jayakumaran Sivagnaname
IPC分类号： G01R27/28
CPC分类号： G11C29/50 , G01R31/31937 , G11C29/50012 , G11C2029/1202 , G11C2029/1204
摘要： A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.
摘要翻译： 用于评估存储单元访问时间的字线到位线定时环形振荡器电路提供关于内部位线访问定时的数据，特别是总字线选择到位线读出输出定时。 存储阵列的列以环形连接，形成环形振荡器。 每列的位线读取电路输出连接到下一列的字线选择输入，环绕环反转，从而形成环形振荡器。 环形振荡器的振荡周期由第一相的总字线选择到位线读取电路输出定时和另一相的预充电间隔时间决定，而位线读取时序主导。 该电路可以应用于小信号存储阵列，其中包括在环形振荡器周期内的读出放大器定时，或者包括读取评估电路时序的大信号存储阵列。
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3.发明授权公开(公告)号：US07668037B2
公开(公告)日：2010-02-23
申请号：US11935566
申请日：2007-11-06
申请人： Gary D. Carpenter , Fadi H. Gebara , Jerry C. Kao , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Fadi H. Gebara , Jerry C. Kao , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C29/02 , G11C29/023 , G11C29/14 , G11C29/50 , G11C29/50012
摘要： A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaluate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.
摘要翻译： 包括具有可编程时序的本地时钟缓冲器的存储阵列提供了用于评估存储阵列内部的电路定时的机制。 本地时钟缓冲器可以独立调节控制字线和本地位线预充电脉冲的本地时钟的脉冲宽度以及控制全局位线预充电，评估和读取数据锁存的延迟时钟的脉冲宽度。 本地时钟和延迟时钟之间的延迟也可以调整。 通过改变本地和延迟的时钟信号的脉冲宽度以及时钟间延迟，可以通过读取和写入具有变化的脉冲宽度和时钟延迟的单元来评估阵列中每个单元的定时裕度。 所得到的评估可用于评估管芯内的时间裕度变化，以及在管芯到管芯之间以及在变化的环境（例如电压和温度变化）下的变化。
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4.发明申请公开(公告)号：US20090116312A1
公开(公告)日：2009-05-07
申请号：US11935566
申请日：2007-11-06
申请人： Gary D. Carpenter , Fadi H. Gebara , Jerry C. Kao , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Fadi H. Gebara , Jerry C. Kao , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C29/02 , G11C29/023 , G11C29/14 , G11C29/50 , G11C29/50012
摘要： A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaulate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.
摘要翻译： 包括具有可编程时序的本地时钟缓冲器的存储阵列提供了用于评估存储阵列内部的电路定时的机制。 本地时钟缓冲器可以独立调节控制字线和本地位线预充电脉冲的本地时钟的脉冲宽度以及控制全局位线预充电，延迟和读取数据锁存的延迟时钟的脉冲宽度。 本地时钟和延迟时钟之间的延迟也可以调整。 通过改变本地和延迟的时钟信号的脉冲宽度以及时钟间延迟，可以通过读取和写入具有变化的脉冲宽度和时钟延迟的单元来评估阵列中每个单元的定时裕度。 所得到的评估可用于评估管芯内的时间裕度变化，以及在管芯到管芯之间以及在变化的环境（例如电压和温度变化）下的变化。
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5.发明申请公开(公告)号：US20080225615A1
公开(公告)日：2008-09-18
申请号：US12128526
申请日：2008-05-28
IPC分类号： G11C29/00
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译： 用于存储单元读取定时评估的脉冲环形振荡器电路提供读取强度信息。 脉冲发生器耦合到待测量的存储单元连接到的位线。 因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。 在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。 或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。 脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。 读取电流是电流之间的差异。
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6.发明授权Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator 有权使用本地时钟发生器的自定时校准优化扩展电压或过程范围内的SRAM性能公开(公告)号：US07864625B2
公开(公告)日：2011-01-04
申请号：US12244286
申请日：2008-10-02
CPC分类号： G11C11/417 , G11C7/22 , G11C11/419
摘要： A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.
摘要翻译： 延迟电路具有在较低电压电平的固定延迟路径，电平转换器和在较高电压电平下的可调延迟路径。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。 这些电压可以响应于动态电压缩放而变化，需要重新校准可调延迟路径。 可调整的延迟路径可以通过逐渐增加SRAM阵列的读取访问时间来校准，直到同时读取操作返回正确的输出，或者通过使用复制SRAM路径来模拟延迟随电压变化的变化。
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7.发明申请Optimizing Sram Performance over Extended Voltage or Process Range Using Self-Timed Calibration of Local Clock Generator 有权使用本地时钟发生器的自定时校准优化扩展电压或过程范围的串行性能公开(公告)号：US20100085823A1
公开(公告)日：2010-04-08
申请号：US12244286
申请日：2008-10-02
CPC分类号： G11C11/417 , G11C7/22 , G11C11/419
摘要： A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.
摘要翻译： 延迟电路具有在较低电压电平的固定延迟路径，电平转换器和在较高电压电平下的可调延迟路径。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。 这些电压可以响应于动态电压缩放而变化，需要重新校准可调延迟路径。 可调整的延迟路径可以通过逐渐增加SRAM阵列的读取访问时间来校准，直到同时读取操作返回正确的输出，或者通过使用复制SRAM路径来模拟延迟随电压变化的变化。
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8.发明授权公开(公告)号：US07409305B1
公开(公告)日：2008-08-05
申请号：US11682542
申请日：2007-03-06
IPC分类号： G06F3/01
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A methor for storage cell read timing evaluation provides read strength information by using a pulsed ring oscillator. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译： 用于存储单元读取定时评估的方法通过使用脉冲环形振荡器来提供读取强度信息。 脉冲发生器耦合到待测量的存储单元连接到的位线。 因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。 在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。 或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。 脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。 读取电流是电流之间的差异。
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9.发明授权公开(公告)号：US07620510B2
公开(公告)日：2009-11-17
申请号：US12128526
申请日：2008-05-28
IPC分类号： G06F3/00
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译： 用于存储单元读取定时评估的脉冲环形振荡器电路提供读取强度信息。 脉冲发生器耦合到待测量的存储单元连接到的位线。 因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。 在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。 或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。 脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。 读取电流是电流之间的差异。
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10.发明授权公开(公告)号：US08576000B2
公开(公告)日：2013-11-05
申请号：US13217349
申请日：2011-08-25
IPC分类号： H01L25/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.
摘要翻译： 提供了一种时钟分配网络，用于在具有两个或更多个层的3D芯片堆栈内同步全局时钟信号。 时钟分配网络包括多个时钟分配电路，每个时钟分配电路被布置在两个或更多个层中的相应一个上，用于将全局时钟信号提供给各种芯片位置。 多个时钟分配电路中的每一个包括用于为时钟分配网络提供层间层耦合的谐振电路。 谐振电路包括至少一个电容器和至少一个电感器。
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