Invention Grant
US07767512B2 Methods of manufacturing a semiconductor device including CMOS transistor having different PMOS and NMOS gate electrode structures
有权
制造包括具有不同PMOS和NMOS栅电极结构的CMOS晶体管的半导体器件的方法
- Patent Title: Methods of manufacturing a semiconductor device including CMOS transistor having different PMOS and NMOS gate electrode structures
- Patent Title (中): 制造包括具有不同PMOS和NMOS栅电极结构的CMOS晶体管的半导体器件的方法
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Application No.: US12019449Application Date: 2008-01-24
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Publication No.: US07767512B2Publication Date: 2010-08-03
- Inventor: Hyung-Suk Jung , Jong-Ho Lee , Sung-Kee Han , Yun-Ki Choi , Ha Jin Lim
- Applicant: Hyung-Suk Jung , Jong-Ho Lee , Sung-Kee Han , Yun-Ki Choi , Ha Jin Lim
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2007-0007278 20070124
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel.
Public/Granted literature
- US20080261360A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE Public/Granted day:2008-10-23
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