Invention Grant
- Patent Title: Method for fabricating semiconductor chip
- Patent Title (中): 制造半导体芯片的方法
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Application No.: US12160143Application Date: 2007-10-05
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Publication No.: US07767551B2Publication Date: 2010-08-03
- Inventor: Kiyoshi Arita , Hiroshi Haji
- Applicant: Kiyoshi Arita , Hiroshi Haji
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Pearne & Gordon LLP
- Priority: JP2006-274938 20061006
- International Application: PCT/JP2007/070016 WO 20071005
- International Announcement: WO2008/044778 WO 20080417
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
After a film layer 6 formed from a die attach film 4 and a UV tape 5 has been provided as a mask on a semiconductor wafer 1, boundary trenches 7 for partitioning semiconductor elements 2 formed on a circuit pattern formation surface 1a are formed in the film layer 6, thereby making a surface 1c of a semiconductor wafer 1 exposed. The exposed surface 1c of the semiconductor wafer 1 in the boundary trenches 7 is etched by means of plasma of a fluorine-based gas, and the semiconductor wafer 1 is sliced into semiconductor chips 1′ along the boundary trenches 7.
Public/Granted literature
- US20090004780A1 Method for Fabricating Semiconductor Chip Public/Granted day:2009-01-01
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