Invention Grant
- Patent Title: Silicided metal gate for multi-threshold voltage configuration
- Patent Title (中): 硅化金属栅极,用于多阈值电压配置
-
Application No.: US11728809Application Date: 2007-03-27
-
Publication No.: US07768072B2Publication Date: 2010-08-03
- Inventor: Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
- Applicant: Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L29/94
- IPC: H01L29/94

Abstract:
A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.
Public/Granted literature
- US20080237750A1 Silicided metal gate for multi-threshold voltage configuration Public/Granted day:2008-10-02
Information query
IPC分类: