Invention Grant
- Patent Title: Non-volatile memory erase verify
- Patent Title (中): 非易失性存储器擦除验证
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Application No.: US11502317Application Date: 2006-08-09
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Publication No.: US07768835B2Publication Date: 2010-08-03
- Inventor: Akira Goda
- Applicant: Akira Goda
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G11C16/06
- IPC: G11C16/06

Abstract:
A memory device having memory cells fabricated in a substrate well is described. The memory device includes control circuitry to perform an erase operation on the memory cells and a voltage bias circuit to bias the substrate well to a positive voltage level during an erase verification operation of memory cells. The voltage bias circuit controls a discharge level of the substrate well following the erase operation to prevent the substrate well from fully discharging lower than the positive voltage level.
Public/Granted literature
- US20080037307A1 Non-volatile memory erase verify Public/Granted day:2008-02-14
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