An integrated circuit 2 includes a plurality of serial data transmitters 18 and a plurality of serial data receivers 20. On-chip test signal paths 22 with associated on-chip test circuits 24, 26, 28 are provided so as to permit on-chip serial data communication to be performed with test characteristics imposed by the on-chip test circuits 24, 26, 28 thereby providing on-chip stress testing of the data transmitter 18 and the serial data receiver 20.