发明授权
- 专利标题: Semiconductor device with large blocking voltage and method of manufacturing the same
- 专利标题(中): 具有大阻断电压的半导体器件及其制造方法
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申请号: US12533740申请日: 2009-07-31
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公开(公告)号: US07772613B2公开(公告)日: 2010-08-10
- 发明人: Haruka Shimizu , Natsuki Yokoyama
- 申请人: Haruka Shimizu , Natsuki Yokoyama
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: Mattingly & Malur, P.C.
- 优先权: JP2008-200397 20080804
- 主分类号: H01L29/80
- IPC分类号: H01L29/80
摘要:
A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of a first epitaxial layer to be a drift layer. The channel region is formed of a first region in which a channel width is constant and a second region below the first region in which the channel width becomes wider toward the drain (substrate) side. A boundary between the first epitaxial layer and the second epitaxial layer is positioned in the second region in which the channel width becomes wider toward the drain (substrate) side.
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